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1. uart-register-file-spartan7 uart-register-file-spartan7 Public

   UART-controlled 8-bit register file implemented on a Spartan-7 FPGA with hexadecimal output on a 7-segment display.

   Verilog 1

2. 16-bit-RISC-ALU-FPGA 16-bit-RISC-ALU-FPGA Public

   16-bit RISC ALU with memory-mapped architecture implemented in Verilog on Spartan-7 FPGA with UART interface and signed overflow detection.

   Verilog 1