- 🔬 Passionate about VLSI Design & Hardware Verification
- 🧠 Working with UVM, AXI Protocols, SystemVerilog
- 🏗️ Experience in CMOS circuit design using Cadence Virtuoso
- 🚀 Built complete AXI4-Lite UVM verification environment
- 💻 Also skilled in Full Stack Development (MERN + Django)
- UVM (Universal Verification Methodology)
- AXI4-Lite Protocol Verification
- SystemVerilog (RTL + Testbench)
- Functional Coverage & Assertions (SVA)
- Timing-aware Driver/Monitor Design
- Debugging handshake & protocol issues (real waveform-level debugging)
- Cadence Virtuoso
- CMOS Logic Design
- Delay Optimization (Reduced ~22% critical path)
- Shannon Decomposition & MUX-based Architectures
- Transient & Timing Analysis
- Developed full UVM testbench:
- Driver, Sequencer, Monitor, Scoreboard
- Functional coverage + SVA assertions
- Debugged real protocol issues:
- Handshake timing bugs
bvalidinstability & race conditions
- Generated waveform-based validation (QuestaSim)
- Designed optimized logic circuits in Cadence Virtuoso
- Applied parallel MUX tree architecture
- Achieved ~22% delay reduction (1007ps → 784ps)
- Full-stack platform (React + Node + MongoDB)
- Integrated prescription & medicine workflow
- Used Cloudinary for image storage
SystemVerilog UVM AXI Cadence Virtuoso QuestaSim
C C++ Python JavaScript
React Node.js Express MongoDB Django Tailwind
Git Linux Postman
- 🔥 Advanced UVM-based verification environments
- 📈 Functional coverage closure strategies
- ⚡ Protocol-level debugging & assertions
- 🌐 Exploring 3D web (Three.js) as secondary skill
- UVM Testbench Design
- AXI Protocol Debugging
- SystemVerilog Assertions
- CMOS Optimization
⭐ "From transistors to testbenches to full-stack systems."