RISC-V-Implementation-

RISC-V Implementation using Verilog for my Computer Organization and Assembly Language Programming course

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
README.md		README.md
alu.v		alu.v
alu_control.v		alu_control.v
alu_control_tb.v		alu_control_tb.v
alu_tb.v		alu_tb.v
control.v		control.v
control_tb.v		control_tb.v
data_mem.v		data_mem.v
data_mem_tb.v		data_mem_tb.v
immgen.v		immgen.v
immgen_tb.v		immgen_tb.v
ins_mem.v		ins_mem.v
ins_mem_tb.v		ins_mem_tb.v
pc.v		pc.v
pc_tb.v		pc_tb.v
processor.v		processor.v
processor.vcd		processor.vcd
processor.vcp		processor.vcp
processor.vvp		processor.vvp
processor_tb.v		processor_tb.v
registers.v		registers.v
registers_tb.v		registers_tb.v

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