Chore/update oss cad suite integration#200
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hendrikmennen merged 2 commits intoone-ware:mainfrom Mar 30, 2026
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hendrikmennen
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Mar 30, 2026
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Small fixes and improvments:
Added Exit Button to Main Menu / File.
Added openFpgaLoaderLongTermFlags and openFpgaLoaderShortTermFlags for FPGA devices.
Fixed one-ware/OneWare.GhdlExtension#26: Now only sets GHDL_PATH on Linux and Darwin for the OSS-CAD-Suite.
Added internal Verilog input folder gen_verilog to the build process. This enables the ability to have Verilog-generated pre-build steps in the plugin while still using the default toolchain.
Top-level entities previously used the whole relative project path in the Yosys -top call. This has been changed to use only the name of the file/module.
Cleaned up comments and imports.