[RISCV] CodeGen Support for XCVsimd Intrinsics#106
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realqhc wants to merge 2 commits intoopenhwgroup:developmentfrom
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[RISCV] CodeGen Support for XCVsimd Intrinsics#106realqhc wants to merge 2 commits intoopenhwgroup:developmentfrom
realqhc wants to merge 2 commits intoopenhwgroup:developmentfrom
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…ype to existing codegen patterns Add RVP vector types to GPR and explict type to existing codegen patterns which couldn't infer all types. From: https://reviews.llvm.org/D100288
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Code generation from simple
add <4 x i8> %a, %bis working right now, however it seems that RVV extension supports VP operations. I am working on bringing support for VP operations to XCVsimd.