Adding support for Qmtech Kintex-7 dev board.#1601
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MIG .prj file was generated in Vivado. Digilent SD card Pmod is assumed in J13. Running at 40 MHz (not fully meeting constraints but boots without issues). Board: http://www.aliexpress.com/item/1005006765717166.html
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Pull request overview
Adds a new FPGA/Linux configuration target to run the Wally SoC on the Qmtech Kintex-7 (xc7k325t) development board, including Vivado IP generation and board-specific constraints/device-tree.
Changes:
- Introduces a new
fpgaTopQmtechk7top-level and Vivado generator targets/scripts forqmtechk7(MMCM + DDR3 MIG). - Adds a Qmtech-specific XDC constraints file and Linux device tree for booting at 40 MHz with 256 MB DDR3.
- Extends the config derivation list to include
fpgaqmtechk7.
Reviewed changes
Copilot reviewed 12 out of 12 changed files in this pull request and generated 9 comments.
Show a summary per file
| File | Description |
|---|---|
| linux/devicetree/wally-qmtechk7.dts | New device tree describing the qmtechk7 memory map and peripherals at 40 MHz. |
| fpga/src/fpgaTopQmtechk7.sv | New FPGA top-level integrating Wally SoC + DDR3 MIG + clocking for qmtechk7. |
| fpga/generator/xlnx_ddr3-qmtechk7-mig.prj | MIG project settings for the qmtechk7 DDR3 configuration. |
| fpga/generator/wally.tcl | Adds qmtechk7 selection for top + constraints + DDR3/MMCM IP import. |
| fpga/generator/sysrst.tcl | Skips board_part assignment for non-Xilinx qmtechk7 board identifier. |
| fpga/generator/mmcm-qmtechk7.tcl | New MMCM IP configuration for 50 MHz input and required output clocks. |
| fpga/generator/Makefile | Adds qmtechk7 make targets for IP generation and FPGA build flow. |
| fpga/generator/ddr3-qmtechk7.tcl | New DDR3 MIG IP generation script using the qmtechk7 MIG .prj. |
| fpga/generator/clkconverter.tcl | Skips board_part assignment for qmtechk7. |
| fpga/generator/ahbaxibridge.tcl | Skips board_part assignment for qmtechk7. |
| fpga/constraints/constraints-qmtechk7.xdc | New board constraints for clocks, IO pinout, SD, UART, DDR3. |
| config/derivlist.txt | Adds fpgaqmtechk7 derivation entry and external memory range. |
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| set_property IOSTANDARD LVCMOS33 [get_ports default_50mhz_clk] | ||
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| # Clocks and Resets (adjust to match board) | ||
| set_property IOSTANDARD LVCMOS33 [get_ports default_200mhz_clk] |
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| create_clock -period 5.000 -name sys_clk [get_ports sys_clk_i] | ||
| create_clock -period 5.000 -name idelay_refclk [get_ports clk_ref_i] | ||
| #create_clock -period 5.000 -name mig_clk_200m [get_ports sys_clk_i] |
| create_clock -period 5.000 -name idelay_refclk [get_ports clk_ref_i] | ||
| #create_clock -period 5.000 -name mig_clk_200m [get_ports sys_clk_i] | ||
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| set_property CLOCK_BUFFER_TYPE BUFG [get_nets wallypipelinedsoc/clk_out3_mmcm] |
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| set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}] | ||
| set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[16]}] | ||
| set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[17]}] | ||
| set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[18]}] | ||
| set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[19]}] | ||
| set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[20]}] | ||
| set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[21]}] | ||
| set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[22]}] | ||
| set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[23]}] | ||
| set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[24]}] | ||
| set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[25]}] | ||
| set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[26]}] | ||
| set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[27]}] | ||
| set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[28]}] | ||
| set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[29]}] | ||
| set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[30]}] |
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| set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[2]}] | ||
| set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[3]}] | ||
| set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}] |
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| set_property PACKAGE_PIN AF3 [get_ports ddr3_odt[0]] | ||
| set_property PACKAGE_PIN AC3 [get_ports ddr3_ras_n] | ||
| set_property W4 [get_ports ddr3_reset_n] |
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| assign GPIOIN = {25'b0, SDCCD, SDCWP, 1'b0, GPI}; | ||
| assign ahblite_resetn = peripheral_aresetn; | ||
| assign cpu_reset = bus_struct_reset; | ||
| assign calib = c0_init_calib_complete; | ||
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| logic [3:0] SDCCSin; | ||
| assign SDCCS = SDCCSin[0]; |
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| .ddr3_reset_n(ddr3_reset_n), | ||
| .ddr3_ck_p(ddr3_ck_p), | ||
| .ddr3_ck_n(ddr3_ck_n), | ||
| .ddr3_cke(ddr3_cke), | ||
| // ddr3_cs_n: always pulled down in this board? | ||
| .ddr3_dm(ddr3_dm), | ||
| .ddr3_odt(ddr3_odt), |
| @@ -0,0 +1,154 @@ | |||
| <?xml version="1.0" encoding="UTF-8" standalone="no" ?> | |||
Contributor
|
@juanschroeder would you be able to review the Copilot feedback above and click resolve conversation on each item when you are satisfied it is either fixed or irrelevant? I don't have the FPGA expertise to review this well and Rose is not very active reviewing right now, but this is valuable work worth incorporating, so I will merge it when you have resolved the copilot feedback. |
Contributor
Author
|
Hi @davidharrishmc , yes, I will look into this after I finish the Nexys A7 one. |
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MIG .prj file was generated in Vivado.
Digilent SD card Pmod is assumed in J13.
Running at 40 MHz (not fully meeting constraints
but boots without issues).
Board: http://www.aliexpress.com/item/1005006765717166.html