tests/unit: add hierarchical_barrier correctness test#62
Draft
bcmIntc wants to merge 1 commit into
Draft
Conversation
Four-subtest correctness suite for shmem_barrier_all(): write visibility, successive barriers (pSync reset stress), asymmetric PE arrival, and atomic counter consistency across rounds. Valid on any build; specifically targets the hierarchical barrier enabled by --enable-hierarchical-barrier. Usage: hierarchical_barrier [-v] [-l <loops>] Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
3778cac to
b6c8ea8
Compare
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Summary
--enable-hierarchical-barrier in the SOS library. The test is also valid and meaningful on non-hierarchical builds.
all puts are globally visible.
before call N's slot is cleared, causing a hang or spurious early completion.
tree gather path under real timing skew.
updates that would indicate CPU/NIC coherency hazards or barrier ordering failures.
Test plan