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    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      Other
      196738259Updated Apr 27, 2026Apr 27, 2026
    • magia-sdk

      Public
      C
      9507Updated Apr 27, 2026Apr 27, 2026
    • auteur

      Public
      The avant-garde tensor unit?
      SystemVerilog
      Other
      0100Updated Apr 27, 2026Apr 27, 2026
    • AraXL

      Public
      A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors
      C
      Other
      5711Updated Apr 27, 2026Apr 27, 2026
    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      SystemVerilog
      Other
      11222637Updated Apr 27, 2026Apr 27, 2026
    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      Apache License 2.0
      4414957Updated Apr 27, 2026Apr 27, 2026
    • C
      3304Updated Apr 27, 2026Apr 27, 2026
    • MAGIA

      Public
      Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.
      C
      Apache License 2.0
      619103Updated Apr 27, 2026Apr 27, 2026
    • hci

      Public
      Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
      SystemVerilog
      Other
      201657Updated Apr 27, 2026Apr 27, 2026
    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      Apache License 2.0
      101130176Updated Apr 26, 2026Apr 26, 2026
    • RISC-V Opcodes
      Python
      Other
      363903Updated Apr 26, 2026Apr 26, 2026
    • control-pulp

      Public
      C
      Other
      4913Updated Apr 24, 2026Apr 24, 2026
    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      C
      Other
      182511919Updated Apr 24, 2026Apr 24, 2026
    • udma_filter

      Public
      A uDMA peripheral to allow memory to memory transfers and linear algebra operations
      SystemVerilog
      7300Updated Apr 23, 2026Apr 23, 2026
    • cv32e40p

      Public
      CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
      SystemVerilog
      Other
      5272000Updated Apr 23, 2026Apr 23, 2026
    • SystemVerilog
      Other
      161713Updated Apr 23, 2026Apr 23, 2026
    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      Other
      9342218Updated Apr 23, 2026Apr 23, 2026
    • bender

      Public
      A dependency management tool for hardware projects.
      Rust
      Apache License 2.0
      59365249Updated Apr 22, 2026Apr 22, 2026
    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      SystemVerilog
      Other
      3531.6k5221Updated Apr 22, 2026Apr 22, 2026
    • gwaihir

      Public
      aka Lago-Mio
      C
      Other
      1202Updated Apr 22, 2026Apr 22, 2026
    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      Verilog
      Other
      1063321822Updated Apr 22, 2026Apr 22, 2026
    • SystemVerilog
      Other
      101911Updated Apr 22, 2026Apr 22, 2026
    • hyperbus

      Public
      SystemVerilog
      Other
      83636Updated Apr 21, 2026Apr 21, 2026
    • pulp-sdk

      Public
      C
      Apache License 2.0
      831241910Updated Apr 20, 2026Apr 20, 2026
    • chimera

      Public
      Python
      Apache License 2.0
      92493Updated Apr 17, 2026Apr 17, 2026
    • cvfpu

      Public
      Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
      SystemVerilog
      Apache License 2.0
      1551906Updated Apr 17, 2026Apr 17, 2026
    • Python
      Apache License 2.0
      41110Updated Apr 17, 2026Apr 17, 2026
    • C++
      17k1471Updated Apr 17, 2026Apr 17, 2026
    • This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
      SystemVerilog
      Other
      1954751317Updated Apr 16, 2026Apr 16, 2026
    • clic

      Public
      RISC-V fast interrupt controller
      SystemVerilog
      Apache License 2.0
      53474Updated Apr 16, 2026Apr 16, 2026
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