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    322 repositories

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •196•738•25•9•Updated Apr 27, 2026Apr 27, 2026

    • magia-sdk

      Public
      C
      •9•5•0•7•Updated Apr 27, 2026Apr 27, 2026

    • auteur

      Public
      The avant-garde tensor unit?
      SystemVerilog
      •
      Other
      •0•1•0•0•Updated Apr 27, 2026Apr 27, 2026

    • AraXL

      Public
      A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors
      C
      •
      Other
      •5•7•1•1•Updated Apr 27, 2026Apr 27, 2026

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilog
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •112•226•3•7•Updated Apr 27, 2026Apr 27, 2026

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •44•149•5•7•Updated Apr 27, 2026Apr 27, 2026

    • ManyRVData

      Public
      C
      •3•3•0•4•Updated Apr 27, 2026Apr 27, 2026

    • MAGIA

      Public
      Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.
      C
      •
      Apache License 2.0
      •6•19•10•3•Updated Apr 27, 2026Apr 27, 2026

    • hci

      Public
      Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
      SystemVerilog
      •
      Other
      •20•16•5•7•Updated Apr 27, 2026Apr 27, 2026

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •101•130•17•6•Updated Apr 26, 2026Apr 26, 2026

    • riscv-opcodes

      Public
      RISC-V Opcodes
      Python
      •
      Other
      •363•9•0•3•Updated Apr 26, 2026Apr 26, 2026

    • control-pulp

      Public
      C
      •
      Other
      •4•9•1•3•Updated Apr 24, 2026Apr 24, 2026

    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      asiccpuvector
      asiccpuvectorriscvararvvrv64gcv
      C
      •
      Other
      •182•511•91•9•Updated Apr 24, 2026Apr 24, 2026

    • udma_filter

      Public
      A uDMA peripheral to allow memory to memory transfers and linear algebra operations
      SystemVerilog
      •7•3•0•0•Updated Apr 23, 2026Apr 23, 2026

    • cv32e40p

      Public
      CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
      SystemVerilog
      •
      Other
      •527•20•0•0•Updated Apr 23, 2026Apr 23, 2026

    • cluster_interconnect

      Public
      SystemVerilog
      •
      Other
      •16•17•1•3•Updated Apr 23, 2026Apr 23, 2026

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •934•22•1•8•Updated Apr 23, 2026Apr 23, 2026

    • bender

      Public
      A dependency management tool for hardware projects.
      Rust
      •
      Apache License 2.0
      •59•365•24•9•Updated Apr 22, 2026Apr 22, 2026

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardware
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •353•1.6k•52•21•Updated Apr 22, 2026Apr 22, 2026

    • gwaihir

      Public
      aka Lago-Mio
      C
      •
      Other
      •1•2•0•2•Updated Apr 22, 2026Apr 22, 2026

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicfpgasimulation
      asicfpgasimulationriscvsystemverilogrtl-design
      Verilog
      •
      Other
      •106•332•18•22•Updated Apr 22, 2026Apr 22, 2026

    • dram_rtl_sim

      Public
      SystemVerilog
      •
      Other
      •10•19•1•1•Updated Apr 22, 2026Apr 22, 2026

    • hyperbus

      Public
      SystemVerilog
      •
      Other
      •8•36•3•6•Updated Apr 21, 2026Apr 21, 2026

    • pulp-sdk

      Public
      C
      •
      Apache License 2.0
      •83•124•19•10•Updated Apr 20, 2026Apr 20, 2026

    • chimera

      Public
      Python
      •
      Apache License 2.0
      •9•24•9•3•Updated Apr 17, 2026Apr 17, 2026

    • cvfpu

      Public
      Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
      SystemVerilog
      •
      Apache License 2.0
      •155•19•0•6•Updated Apr 17, 2026Apr 17, 2026

    • pulp-actions

      Public
      Python
      •
      Apache License 2.0
      •4•11•1•0•Updated Apr 17, 2026Apr 17, 2026

    • llvm-project

      Public
      C++
      •17k•14•7•1•Updated Apr 17, 2026Apr 17, 2026

    • pulpissimo

      Public
      This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
      SystemVerilog
      •
      Other
      •195•475•131•7•Updated Apr 16, 2026Apr 16, 2026

    • clic

      Public
      RISC-V fast interrupt controller
      interruptrisc-vclic
      interruptrisc-vclic
      SystemVerilog
      •
      Apache License 2.0
      •5•34•7•4•Updated Apr 16, 2026Apr 16, 2026
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