Simulation Package Submission#3
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Fixed dv flow so that can successfully run `make cocotb-verify-all-rtl` and get the expected success. The problems were diagnosed to be: - Extra test in `user_proj_tests/user_proj_tests.yaml` - Incorrect wrapper name for the behavioral model in the (gitignored) ip directory.
Updated `README.md` with slightly adjusted design.
(Claude) Created RTL, testbench for the 8x8 byte matrix mulitplication accelerator.
With Claude Code, fixed various parts of the matrix multiplication accelerator, including: - Added a `STICKY_DONE` bit to allow for reasonable polling timings. - Modified `CYCLES` to be similarly sticky. - Utilized simulation waveforms to diagnose systolic array delay mismatch; chose to simply use single-delay processing elements. While this might increase the critical path due to MAC occurring in one clock cycle, the design is already limited by the Caravel SoC max clock speed.
Added venv-cocotb to .gitignore for cleaner development histories.
Moved simulation artifacts from the `.gitignore`d directories to the main directory, under `artifacts`. Also added a brief explanation through a `README.md` in that directory.
Added AI/LLM transcripts used in the design process.
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GDS soon to come! |
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Submission for the ChipFoundry NVM Power-Up Design Contest simulation package that is due before November 3rd, SGT.
Contains test harness, RTL, artifacts (including evidence of local simulation), and instructions on replicating on other machines.