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PS-11167: Add DISTANCE() for VECTOR data type#5975

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PS-11167: Add DISTANCE() for VECTOR data type#5975
catalinbp wants to merge 1 commit into
percona:trunkfrom
catalinbp:ps-11167

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Implement SQL DISTANCE(vector, vector, metric) and the VECTOR_DISTANCE() synonym for vector similarity queries. Supported metrics: EUCLIDEAN (L2), MANHATTAN (L1), COSINE, and DOT.

Core library (vector-common/vector_distance.*):

  • Runtime SIMD dispatch across Scalar, SSE4.2/NEON, AVX2, AVX-512F, and SVE2 tiers; per-kernel target attributes, no global -march=native
  • Dim-aware wide/narrow dispatch (dims >= 16 use widest tier; smaller vectors use 128-bit tier to avoid AVX setup overhead)
  • Unaligned load intrinsics throughout: VECTOR data may be misaligned (e.g. SUBSTR blobs); on modern CPUs unaligned and aligned loads have identical throughput when data is aligned; aligned loads would fault on misaligned inputs without a performance benefit. Loads that span a 64-byte cache-line boundary may still be slower (two line fetches); that depends on runtime address, not on loadu vs load, and is not avoided by switching to aligned intrinsics
  • Float32 SIMD accumulation with double-precision horizontal sum and scalar tail: preserves correctness for large dimensions and extreme values (e.g. 2e38 Euclidean distance) without sacrificing SIMD width
  • Manhattan (L1): sum of absolute differences;

Implement SQL DISTANCE(vector, vector, metric) and the VECTOR_DISTANCE()
synonym for vector similarity queries. Supported metrics:
EUCLIDEAN (L2), MANHATTAN (L1), COSINE, and DOT.

Core library (vector-common/vector_distance.*):
- Runtime SIMD dispatch across Scalar, SSE4.2/NEON, AVX2, AVX-512F, and
  SVE2 tiers; per-kernel target attributes, no global -march=native
- Dim-aware wide/narrow dispatch (dims >= 16 use widest tier; smaller
  vectors use 128-bit tier to avoid AVX setup overhead)
- Unaligned load intrinsics throughout: VECTOR data may be misaligned
  (e.g. SUBSTR blobs); on modern CPUs unaligned and aligned loads have
  identical throughput when data is aligned; aligned loads would fault
  on misaligned inputs without a performance benefit.  Loads that span
  a 64-byte cache-line boundary may still be slower (two line fetches);
  that depends on runtime address, not on loadu vs load, and is not
  avoided by switching to aligned intrinsics
- Float32 SIMD accumulation with double-precision horizontal sum and
  scalar tail: preserves correctness for large dimensions and extreme
  values (e.g. 2e38 Euclidean distance) without sacrificing SIMD width
- Manhattan (L1): sum of absolute differences;
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