llext: xtensa: improvements for xtensa platform#1
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andreagilardoni wants to merge 2263 commits intopillo79:mainfrom
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llext: xtensa: improvements for xtensa platform#1andreagilardoni wants to merge 2263 commits intopillo79:mainfrom
andreagilardoni wants to merge 2263 commits intopillo79:mainfrom
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pillo79
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General first review comments:
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Zephyr needs to support bisecting so every commit needs to be self-supporting. Support for something must come before or together with the first users of something.
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merge similar commits describing the overall goal: for example [llext: xtensa: harvard based architectures address check] and [llext: xtensa: fixing text section reuse check] must become one, also [arc: llext: custom settings for arc architecture] should be merged or before [llext: heap: section attribute customization].
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we need to understand how to add the information in
arch/arc/include/llext_arch_custom.hfile in a way that is hierarchical. 🤔 ⚙️ 💭
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| #if CONFIG_HARVARD && CONFIG_ARC | ||
| #include <llext_arch_custom.h> | ||
| #endif |
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Not sure how to fix this, but we can't have this kind of per-arch or per-soc logic in llext.
pillo79
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Nov 26, 2025
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| #include <memory.h> | ||
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| #define INSTR_FETCHABLE(base_addr, alloc) \ | ||
| (IN_RANGE((uintptr_t)(base_addr), SRAM1_IRAM_START, SRAM1_IRAM_START + SRAM1_SIZE) && \ | ||
| IN_RANGE((uintptr_t)(base_addr) + alloc, SRAM1_IRAM_START, SRAM1_IRAM_START + SRAM1_SIZE)) |
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This (and the above) need to be moved to the same place as the stuff in arc_custom - where ❓ .
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Enable api and looback test for S32K5 PWM(eMIOS) Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>
… in v1 Commit e7f222a fixed the bug where a data size mismatch produces unexpected behavior with the DMA on V1 devices. However, this limitation is only valid for the STM32 series with V1 DMA, V2 doesn't have this. The STM32CubeMX configuration tool correctly implements this limitation in the UI, it is a good way to cross-check. Signed-off-by: Benedek Kupper <kupper.benedek@gmail.com>
Updates the time slicing image in the associated documentation to ... 1. Show the resetting of a time slice after scheduling a new thread 2. Indicate that it is specific for UP scheduler It also adds a note to the documentation describing how the ordering of the threads would change with the SMP scheduler. Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Adds a short section explaining how thread ordering between UP and SMP systems differ. Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Until now transmission FIFO was not used. With this chamge the FIFO will be filled up, until it is full. Signed-off-by: Daniel Fladerer <d.fladerer@gmx.de>
Since e150ffb, Zephyr only really supports native_simulator based targets when building native/posix arch based targets. So this comment is not relevant anymore. Let's remove it. Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The debug/stack.h header uses k_thread types and APIs such as struct k_thread, k_thread_stack_space_get(), and k_thread_name_get(), but does not include <zephyr/kernel.h>. This makes the header rely on transitive includes, which can lead to build failures depending on include order. Add an explicit include of <zephyr/kernel.h> to make the header self-contained. Signed-off-by: Michele Sardo <msmttchr@gmail.com>
Add a trailing space to the Ruff error message string in the compliance checking script. Previously, the error message concatenated the URL and the description with a colon (e.g., ".../unsorted-imports:Import"). This caused the terminal to interpret the description as part of the URL, resulting in a 404 error when clicked. Signed-off-by: Thamaraimanalan M <devthamaraimanalan.m@gmail.com>
Tested with the commands mentioned in index.rst Product photo from https://www.cytron.io/p-motion-2350-pro Signed-off-by: Jonas Berg <jonas.s.t.berg@gmail.com>
Enabled servo port GP0. Added commented-out entries for the other ports, as is done for the other overlay files. Signed-off-by: Jonas Berg <jonas.s.t.berg@gmail.com>
Add Framework Computer Inc Signed-off-by: Daniel Schaefer <dhs@frame.work>
The following examples build and work as expected. Blink backlight using PWM on white backlight keyboard or numpad: > west build -p -b framework_laptop16_keyboard samples/basic/blinky_pwm Blink capslock on keyboard (not numpad or macropad): > west build -p -b framework_laptop16_keyboard samples/basic/blinky_pwm > west build -p -b framework_laptop16_keyboard samples/subsys/usb/console > west build -p -b framework_laptop16_keyboard samples/subsys/usb/cdc_acm > west build -p -b framework_laptop16_keyboard samples/drivers/adc/adc_dt Signed-off-by: Daniel Schaefer <dhs@frame.work>
Update Zephyr fork of MCUboot to revision:
9ac72969f281491d677e669d053281fc2d538ed4
Brings following Zephyr relevant fixes:
- 9ac72969 boot: bootutil: loader: Fix bootstrap copying in
swap move mode
- 3f69203f bootutil: ed25519 psa: Merge bootutil_verify_sig and
bootutil_verify
- 7f354916 bootutil: Remove bootutil_verify_img
- 7cec4af1 bootutil: Replace bootutil_verify_img with
bootutil_verify_sig
- 4a57d03d boot: zephyr: socs: stm32h7s3xx: Add support for
ext_flash_app variant
- a21fd276 bootutil: Small logging improvements
- 0acc9806 bootutil: boot_read_enc_key now returns boolean
- 553be8b0 readme: Update for next dev release
- eecc3f7d Release v2.3.0
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
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Adding support for arduino nano esp32 Signed-off-by: Andrea Gilardoni <a.gilardoni@arduino.cc>
Harvard architecture refers to a CPU architecture with separate storage and signal pathways for instructions and data. This is in contrast with the more common von Neumann architecture, where program instructions and data share the same address maps. This is already used in the ARC architecture, so this patch adds a common HARVARD config option in arch/Kconfig, and makes ARC's existing HARVARD config option user-selectable. Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
This change marks the Xtensa architecture as having separate code and data paths. This is necessary for proper handling of llext buffers. Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
A valid elf file may contain a relocation section with no relocation to perform, skipping its relocation Signed-off-by: Andrea Gilardoni <a.gilardoni@arduino.cc>
This change aligns xtensa llext link procedure to follow the other architecures linkage flow in favor of code reuse Signed-off-by: Andrea Gilardoni <a.gilardoni@arduino.cc>
This options allows to select the relocation method to perform on xtensa platform. If disable this allows to use the common flow used by other platforms Signed-off-by: Andrea Gilardoni <a.gilardoni@arduino.cc>
llext_loaded_sect_ptr result is not being usend anywhere Signed-off-by: Andrea Gilardoni <a.gilardoni@arduino.cc>
memory.h file in esp32s3 soc definition is missing SRAM1_SIZE Signed-off-by: Andrea Gilardoni <a.gilardoni@arduino.cc>
This commit adds the missing definition of INSTR_FETCHABLE macro that is required for Harvard architectures in order to properly check that the address of an instruction is being accessed on the proper instruction bus Signed-off-by: Andrea Gilardoni <a.gilardoni@arduino.cc>
This commit adds arch_d2i_address and arch_i2d_address which can be used in an harvard based architecture to convert an address from being accessed through the data bus to the instruction bus and vicevers Signed-off-by: Andrea Gilardoni <a.gilardoni@arduino.cc>
The extracted section name is only used when CONFIG_LLEXT_XTENSA_PLT=y or debug logging is enabled Signed-off-by: Andrea Gilardoni <a.gilardoni@arduino.cc>
Adding a file that contains ARC specific customization for llext, i.e. data and instruction heap section attributes definition Signed-off-by: Andrea Gilardoni <a.gilardoni@arduino.cc>
This commit add the possibility of using externally defined section attributes for instr and data heaps for Harvard based architectures Signed-off-by: Andrea Gilardoni <a.gilardoni@arduino.cc>
using arch_d2i_address function for llext to check init function addresess correctly in the ibus space Signed-off-by: Andrea Gilardoni <a.gilardoni@arduino.cc>
converting text section addess to instruction space in order to check correclty for reuse for xtensa architecture Signed-off-by: Andrea Gilardoni <a.gilardoni@arduino.cc>
Added LLEXT_SEPARATE_HEAPS option to disable heap separation on harvard architectures, the default value is enabled Signed-off-by: Andrea Gilardoni <a.gilardoni@arduino.cc>
Nano esp32 board needs specific settings fot llext to work: - LLEXT_XTESA_PLT=n: it has been tested to use the normal flow shared among other architectures instead of xtensa specific PLT - LLEXT_SEPARATE_HEAPS=n: depite being an Harvard architecture a nano esp32 could use a single heap for both data and intructions, in order to improve memory usage
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This PR aims to improve the integration with the xtensa platform, in particular for espressif based boards, like esp32s3 soc.
Main changes:
arch_elf_relocatewith zephyr llext standard flow, optionally available