Request access for fshaked

[fshaked]

Hi,

I'm doing research at University of Cambridge (my page).

I would like to run a suite of concurrency litmus tests on as many multi-core RISC-V SoCs as possible. This will provide essential information to validate the RISC-V memory model, and the HW itself.

Best,
Shaked Flur

[lazyparser]

Welcome! We will prepare your RISC-V machine as soon as possible. Please understand that due to the Chinese New Year holiday starting this week, all logistics and hardware preparation work may be delayed until after the holiday ends on February 24th.

[fshaked]

Thank you, and happy new year.

…

On Wed, 11 Feb 2026 at 18:12, Wei Wu ***@***.***> wrote: *lazyparser* left a comment (plctlab/riscv-lab-access#84) <#84 (comment)> Welcome! We will prepare your RISC-V machine as soon as possible. Please understand that due to the Chinese New Year holiday starting this week, all logistics and hardware preparation work may be delayed until after the holiday ends on February 24th. — Reply to this email directly, view it on GitHub <#84 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ACTBFFCZYFVCNRJQ4M3K2CT4LNPGNAVCNFSM6AAAAACUTR6XLWVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZTQOBVGYZTKMBTGA> . You are receiving this because you authored the thread.Message ID: ***@***.***>

[lazyparser]

Update:

Currently, the leading multi-core RISC-V machine is the SG2044, which features 64 RISC-V cores. Regrettably, however—due to sanctions imposed by the U.S. Department of Commerce—it is currently very difficult to obtain the SG2044. While its predecessor, the SG2042, also possesses 64 cores, it suffers from certain known stability issues and may therefore be unable to meet the demands of rigorous stress testing. The current alternative option is the SpacemiT K1, which features 8 cores and supports RVV. Would the K1 be able to meet your requirements?