Skip to content

[RV64_DYNAREC] Fix the issue where source register values get overwritten. #4032

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
ptitSeb merged 1 commit into from
Jul 13, 2026
+32 −24
Merged

[RV64_DYNAREC] Fix the issue where source register values get overwritten. #4032

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
56 changes: 32 additions & 24 deletions src/dynarec/rv64/dynarec_rv64_f20f.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -205,42 +205,46 @@ uintptr_t dynarec64_F20F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
nextop = F8;
GETGXSD(v0);
GETEXSD(v1, 0);
d0 = fpu_get_scratch(dyn);
if (!BOX64ENV(dynarec_fastnan)) {
FMVD(d0, v1);
FEQD(x3, v1, v1);
FEQD(x4, v0, v0);
AND(x5, x3, x4);
BEQZ(x5, 4 + 4 * 4);
}
FADDD(v1, v1, v0);
FADDD(d0, v1, v0);
if (!BOX64ENV(dynarec_fastnan)) {
FEQD(x5, v1, v1);
BNEZ(x5, 4 + 4);
FNEGD(v1, v1);
FEQD(x5, d0, d0);
BNEZ(x5, 4 + 4 * 3);
FNEGD(d0, d0);
BNEZ(x4, 4 + 4);
FMVD(v1, v0);
FMVD(d0, v0);
}
FMVD(v0, v1);
FMVD(v0, d0);
break;
case 0x59:
INST_NAME("MULSD Gx, Ex");
nextop = F8;
GETGXSD(v0);
GETEXSD(v1, 0);
d0 = fpu_get_scratch(dyn);
if (!BOX64ENV(dynarec_fastnan)) {
FMVD(d0, v1);
FEQD(x3, v1, v1);
FEQD(x4, v0, v0);
AND(x5, x3, x4);
BEQZ(x5, 4 + 4 * 4);
}
FMULD(v1, v1, v0);
FMULD(d0, v1, v0);
if (!BOX64ENV(dynarec_fastnan)) {
FEQD(x5, v1, v1);
BNEZ(x5, 4 + 4);
FNEGD(v1, v1);
FEQD(x5, d0, d0);
BNEZ(x5, 4 + 4 * 3);
FNEGD(d0, d0);
BNEZ(x4, 4 + 4);
FMVD(v1, v0);
FMVD(d0, v0);
}
FMVD(v0, v1);
FMVD(v0, d0);
break;
case 0x5A:
INST_NAME("CVTSD2SS Gx, Ex");
Expand All @@ -260,21 +264,23 @@ uintptr_t dynarec64_F20F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
nextop = F8;
GETGXSD(v0);
GETEXSD(v1, 0);
d0 = fpu_get_scratch(dyn);
if (!BOX64ENV(dynarec_fastnan)) {
FMVD(d0, v1);
FEQD(x3, v1, v1);
FEQD(x4, v0, v0);
AND(x5, x3, x4);
BEQZ(x5, 4 + 4 * 4);
}
FSUBD(v1, v0, v1);
FSUBD(d0, v0, v1);
if (!BOX64ENV(dynarec_fastnan)) {
FEQD(x5, v1, v1);
BNEZ(x5, 4 + 4);
FNEGD(v1, v1);
FEQD(x5, d0, d0);
BNEZ(x5, 4 + 4 * 3);
FNEGD(d0, d0);
BNEZ(x4, 4 + 4);
FMVD(v1, v0);
FMVD(d0, v0);
}
FMVD(v0, v1);
FMVD(v0, d0);
break;
case 0x5D:
INST_NAME("MINSD Gx, Ex");
Expand All @@ -296,21 +302,23 @@ uintptr_t dynarec64_F20F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
nextop = F8;
GETGXSD(v0);
GETEXSD(v1, 0);
d0 = fpu_get_scratch(dyn);
if (!BOX64ENV(dynarec_fastnan)) {
FMVD(d0, v1);
FEQD(x3, v1, v1);
FEQD(x4, v0, v0);
AND(x5, x3, x4);
BEQZ(x5, 4 + 4 * 4);
}
FDIVD(v1, v0, v1);
FDIVD(d0, v0, v1);
if (!BOX64ENV(dynarec_fastnan)) {
FEQD(x5, v1, v1);
BNEZ(x5, 4 + 4);
FNEGD(v1, v1);
FEQD(x5, d0, d0);
BNEZ(x5, 4 + 4 * 3);
FNEGD(d0, d0);
BNEZ(x4, 4 + 4);
FMVD(v1, v0);
FMVD(d0, v0);
}
FMVD(v0, v1);
FMVD(v0, d0);
break;
case 0x5F:
INST_NAME("MAXSD Gx, Ex");
Expand Down
Loading