SPM address scrambling fix, VCS flow update, trace visualization#17
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liyinrong wants to merge 4 commits into
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SPM address scrambling fix, VCS flow update, trace visualization#17liyinrong wants to merge 4 commits into
liyinrong wants to merge 4 commits into
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Pull request overview
Note
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Adds scalable performance visualization and lightweight SPM bank tracing, while refactoring tile-internal TCDM plumbing to reduce simulation overhead and unify address/remap behavior.
Changes:
- Add a new Perfetto protobuf generator (
perfetto_gen.py) and Makefile targets to export/view traces, plus VCS FSDB dump scripting updates. - Introduce lightweight per-bank SPM profiling logs and hook them into the testbench.
- Refactor/replace legacy address scrambler + bank/tile-id remappers and wide/narrow muxing with
mempool_addr_scrambler+mempool_tcdm_bank_interco.
Reviewed changes
Copilot reviewed 22 out of 23 changed files in this pull request and generated 9 comments.
Show a summary per file
| File | Description |
|---|---|
| hardware/tb/tb_spm_profiling.svh | New lightweight per-tile SPM bank run/packet logger. |
| hardware/tb/mempool_tb.sv | Includes the new SPM profiling header in the TB. |
| hardware/src/mempool_tcdm_bank_interco.sv | New unified bank-side interconnect replacing multiple legacy blocks. |
| hardware/src/mempool_addr_scrambler.sv | New combined address scrambler replacing older scrambler + DMA remapper. |
| hardware/src/mempool_tile.sv | Wires in new bank interconnect and new address scrambler; disables heavy profiler. |
| hardware/src/mempool_group.sv | Switches DMA tile select to use mempool_addr_scrambler. |
| hardware/src/tcdm_shim.sv | Removes in-shim tile-id remap logic and related parameters. |
| hardware/src/mempool_pkg.sv | Removes older profiling struct typedefs under profiling guards. |
| hardware/scripts/vcs/run.tcl | Adds full FSDB dump commands and sources the curated wave setup. |
| hardware/scripts/vcs/wave.tcl | Replaces prior loop-heavy wave scripts with a Verdi-safe curated view. |
| hardware/scripts/vcs/dump_all.tcl | New headless FSDB dump script. |
| hardware/scripts/perfetto_gen.py | New tool to create Perfetto traces from dasm + NoC/SPM logs. |
| hardware/Makefile | Adds Verdi toggle, assert args, FSDB sim target, perfetto-gen/view targets. |
| Makefile | Adds installation target for Perfetto trace_processor (shell + container). |
| Bender.yml | Removes deleted legacy sources; adds new scrambler + bank interconnect sources. |
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| // Rotation FIFO: push at fork accept, pop at wide resp out. | ||
| logic [RotBits-1:0] resp_rot; | ||
| logic rot_fifo_push, rot_fifo_pop; | ||
| logic rot_fifo_full; |
| .valid_o(sb_fork_valid ), | ||
| .ready_i(sb_fork_ready ) | ||
| ); | ||
| assign rot_fifo_push = wide_to_sb_valid[d] & wide_to_sb_ready[d]; |
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| always_ff @(posedge clk_i) begin | ||
| if (rst_ni && rot_fifo_push && rot_fifo_full) begin | ||
| $fatal(1, "[mempool_tcdm_bank_interco] sb=%0d rot FIFO overflow (depth=%0d)", d, RotFifoDepth); | ||
| end | ||
| end |
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| localparam int unsigned NumBanksPerSB = NumBanksPerTile / NumSuperbanks, | ||
| localparam int unsigned BankOffsetBits = $clog2(NumBanksPerTile), | ||
| localparam int unsigned BankIdLoBits = $clog2(NumBanksPerSB), |
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| for (genvar i = 0; i < NumNarrowReq; i++) begin : gen_narrow_sel | ||
| logic [BankIdLoBits-1:0] raw_lo, new_lo; | ||
| assign raw_lo = slv_narrow_req_i[i].tgt_addr[0 +: BankIdLoBits]; |
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| // NOTE: bank-id remap is intentionally NOT here — it lives in the tile's | ||
| // bank-side network (mempool_bank_id_remapper). |
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| // Stage 1: sequential→interleaved field swap (sequential region only). | ||
| if (EnableSeqInterleaveSwap && (address_i < (NumTiles * SeqMemSizePerTile))) begin | ||
| address_o[SeqTotalBits-1:ConstantBitsLSB] = {scramble, tile_id}; | ||
| end | ||
| // Stage 2: tile-id remap. Stages 1/2 are mutually exclusive by range. | ||
| else if (EnableTileIdRemap && not_io_address) begin | ||
| address_o[ConstantBitsLSB +: TileIdBitsPerDma] = | ||
| spm_tile_id_remap( | ||
| address_i[ConstantBitsLSB +: TileIdBitsPerDma], | ||
| address_i[(ConstantBitsLSB + TileIdBits) +: TileIdBitsPerDma] | ||
| ); | ||
| end |
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| automatic int unsigned winp = `SPM_TILE(g,t).bank_req_ini_addr[b]; | ||
| $fwrite(f_bank[g][t], "P %0d %0d %0d %0h %0d %0d %0d %0d %0d %0d %0d\n", | ||
| b, cycle_q, | ||
| `SPM_TILE(g,t).bank_req_payload[b].wen, | ||
| `SPM_TILE(g,t).bank_req_payload[b].tgt_addr, | ||
| (winp < NLP) ? 1 : 0, // loc: local port | ||
| `SPM_TILE(g,t).bank_req_wide[b], // wide: DMA access | ||
| winp, // winning input port |
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| $(PERFETTO_SHELL): | ||
| mkdir -p $(PERFETTO_INSTALL_DIR) | ||
| @url=$$(curl -sSL --fail https://get.perfetto.dev/trace_processor | \ | ||
| grep -oE 'https://\S+linux-amd64/trace_processor_shell' | head -1); \ | ||
| test -n "$$url" || { echo "ERROR: cannot resolve latest trace_processor URL"; exit 1; }; \ | ||
| echo ">> latest trace_processor: $$url"; \ | ||
| curl -L --fail -o $@ "$$url" | ||
| chmod +x $@ |
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