Implement Zicfiss and Zicfilp extensions for Control-Flow Integrity

[emanueleparisi]

Implement the Zicfiss and Zicfilp ISA extensions for Control-Flow Integrity.

Zicfiss

The Zicfiss extension introduces a shadow stack to enforce backward-edge control-flow integrity. A shadow stack is a second stack used to store a shadow copy of the return address in the link register if it needs to be spilled. The shadow stack is designed to provide integrity to control transfers performed using a return, where the return may be from a procedure invoked using an indirect call or a direct call, and this is referred to as backward-edge protection. The extension adds the following instructions:

• SSPUSH x1, SSPUSH x5
• C.SSPUSH x1
• SSPOPCHK x1, SSPOPCHK x5
• C.SSPOPCHK x5
• SSRDP
• SSAMOSWAP.W, SSAMOSWAP.D

Zicfilp

To enforce forward-edge control-flow integrity, the Zicfilp extension introduces a landing pad (LPAD) instruction. The LPAD instruction must be placed at the program locations that are valid targets of indirect jumps or calls. The LPAD instruction is encoded using the AUIPC major opcode with rd = x0.

Relevant links:

• RISC-V Control-Flow Integrity Release v1.0-rc1

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	always_comb begin : landingpad_port
	elp_o = elp_i;
	lpl_o = lpl_i;
	commit_ack_o = commit_ack_i;
	we_gpr_o = we_gpr_i;
	lp_fault_o = 'b0;
	end
	always_comb begin : landingpad_port
	elp_o = elp_i;
	lpl_o = lpl_i;
	commit_ack_o = commit_ack_i;
	we_gpr_o = we_gpr_i;
	lp_fault_o = 'b0;
	end

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	menvcfg_q <= menvcfg_d;
	henvcfg_q <= henvcfg_d;
	senvcfg_q <= senvcfg_d;
	menvcfg_q <= menvcfg_d;
	henvcfg_q <= henvcfg_d;
	senvcfg_q <= senvcfg_d;

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	localparam logic [63:0] ENVCFG_FIOM = 64'h0000000000000001;
	localparam logic [63:0] ENVCFG_LPE = 64'h0000000000000004;
	localparam logic [63:0] ENVCFG_SSE = 64'h0000000000000008;
	localparam logic [63:0] ENVCFG_CBIE = 64'h0000000000000030;
	localparam logic [63:0] ENVCFG_CBFE = 64'h0000000000000040;
	localparam logic [63:0] ENVCFG_CBZE = 64'h0000000000000080;
	localparam logic [63:0] ENVCFG_FIOM = 64'h0000000000000001;
	localparam logic [63:0] ENVCFG_LPE = 64'h0000000000000004;
	localparam logic [63:0] ENVCFG_SSE = 64'h0000000000000008;
	localparam logic [63:0] ENVCFG_CBIE = 64'h0000000000000030;
	localparam logic [63:0] ENVCFG_CBFE = 64'h0000000000000040;
	localparam logic [63:0] ENVCFG_CBZE = 64'h0000000000000080;

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	localparam logic [63:0] ENVCFG_STCE = 64'h8000000000000000;
	localparam logic [63:0] ENVCFG_STCE = 64'h8000000000000000;

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	localparam logic [63:0] SECCFG_MML = 64'h0000000000000001;
	localparam logic [63:0] SECCFG_MMWP = 64'h0000000000000002;
	localparam logic [63:0] SECCFG_RLP = 64'h0000000000000004;
	localparam logic [63:0] SECCFG_MML = 64'h0000000000000001;
	localparam logic [63:0] SECCFG_MMWP = 64'h0000000000000002;
	localparam logic [63:0] SECCFG_RLP = 64'h0000000000000004;

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	localparam logic [63:0] SECCFG_MLPE = 64'h0000000000000400;
	localparam logic [63:0] SECCFG_MLPE = 64'h0000000000000400;