Draft: Major updates

[FrancescoConti]

This PR introduces several major changes to PULPissimo:

• support to Verilator simulation
• support for CV3240X (with example FIR XIF unit) as an option
• support for Zybo Z7 board
• non-public synthesis flow

TODO list:

• add more regression tests for Verilator
• add regression tests for more configurations (e.g., with CV32E40X)
• merge changes upstream (pulp_soc and a few others) before merging this PR
• add (minimal) README for Verilator

Some of the changes have been introduced for the EFCL Summer School 2024, whereas others follow it.

[Bogatell4]

Hello, I'm trying to run the same CI tests but running into some verilator problems about unsupported functionalities in the tool. Could you point out which verilator version are you using?
Thx

[FrancescoConti]

Currently, Verilator 5.034 2025-02-24 rev v5.034-47-gac3f30ed6 .
Consider this is still a draft.

[FrancescoConti]

Hello, I'm trying to run the same CI tests but running into some verilator problems about unsupported functionalities in the tool. Could you point out which verilator version are you using? Thx

I checked and the bug you see is reproducible when moving to Verilator 5.036.
It has to do with

pulpissimo/target/sim/tb/tb_pulp.sv

Line 616 in 5a93977

debug_mode_if.init_dmi_access(s_tck, s_tms, s_trstn, s_tdi);

and following lines.