feat(rivet): V-closure traceability gate + promote 16 lagging requirements (v0.6.0 D3) - #228
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feat(rivet): V-closure traceability gate + promote 16 lagging requirements (v0.6.0 D3)#228avrabe wants to merge 1 commit into
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…ments (v0.6.0 D3) The release-completeness gate asks 'does every approved/implemented artifact have its V closed?' — answerable only if requirement statuses track their verification artifacts. They had drifted: 16 requirements carried a 'verified' VER-* while still reading 'implemented'/'proposed' themselves — the whole verified driver suite (adc/can/dac/i2c/pwm/spi/wdg/dma/breadth), gpio, timer, the syscall seam, the executor, DMA-async, I-ISO and tri-track. The gate misreported them as not-done: it erred safe, but it lied, and nothing stopped it recurring. tools/check-v-closure.py fails when a requirement's matching VER-* is 'verified' while the requirement is not (paired by id). Red-tested: it reported exactly those 16 before the fix and is green after. Each promotion was checked against the VER artifact's evidence (Kani counts, Renode content-gates, silicon captures, stated kill-criteria) — not bulk-flipped. rivet validate PASS (334 warnings, unchanged); the diff is exactly 16 status lines. Wired as .github/workflows/rivet-v-closure.yml on artifacts/ changes, so this class of drift cannot recur silently — same shape as the gale#214 WIT-drift gate. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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First workstream of the v0.6.0 plan (#227) — sequenced first deliberately: until the completeness gate tells the truth, "is v0.6.0 cuttable?" isn't a question rivet can answer.
The drift
The release gate asks whether every approved/implemented artifact has its V closed. That's only answerable if requirement statuses track their verification artifacts — and they'd drifted. 16 requirements carried a
verifiedVER-*while still readingimplemented/proposedthemselves:REQ-DRV-{ADC,CAN,DAC,I2C,PWM,SPI,WDG,DMA,BREADTH,GPIO,TIMER}-001·REQ-OS-{SYSCALL,EXEC,ISO,TRITRACK}-001·REQ-DMA-ASYNC-001The gate read all of them as not done. It erred safe — but it misreported, and nothing prevented recurrence.
The gate
tools/check-v-closure.pyfails when a requirement's matchingVER-*(paired by id) isverifiedwhile the requirement is not.V-closure traceability: OK — 22 REQ/VER pairs, no requirement lags its closed V..github/workflows/rivet-v-closure.ymlonartifacts/changes — same shape as the gale#214 WIT-drift gate.The promotions were checked, not bulk-flipped
Each
VER-*was read for real evidence before promoting: Kani harness counts (gpio 4/4, timer 3/3 — confirmed against the driver sources), Renode register-effect content-gates, silicon captures, and stated kill-criteria.REQ-DMA-ASYNC-001(the oneproposed → verifiedjump I trusted least) cites the concretedma_poll_completesplit-phase export, the FSM transition with barrier emission, an unchanged TCB, and its own kill-criterion.rivet validate→ PASS (334 warnings, unchanged). The diff is exactly 16 status lines — nothing else touched.🤖 Generated with Claude Code