finding: REQ-PIX-007 typed-contract is spar-gated — spar emits opaque list<u8> for all AADL data (AFD-036 / spar#345)

artifacts/findings.yaml

@@ -1237,3 +1237,37 @@ artifacts:
         target: EXTERNALANCHOR-002
       - type: traces-to
         target: REQ-PIX-001
+
+  - id: AFD-036
+    type: ai-found-defect
+    title: spar codegen --format wit emits opaque list<u8> for every AADL data type - no structured WIT record/list<f32>, gating REQ-PIX-007's typed inter-core contract
+    status: open
+    description: >
+      Found 2026-07-23 (feature-loop step 2, deriving the inter-core WIT for REQ-PIX-007). The 3-core
+      partition's M4->M7 crossing is a NavState = 16 x f32 (64 B) message (byte-exact crossing PROVEN
+      in TEST-PIX-030). Tried to make the WIT CONTRACT structured (a record / list<f32>) by enriching
+      the AADL VehicleState data type, so the typed ABI reflects the real payload. spar codegen maps
+      EVERY AADL data type to `type X = list<u8>` regardless of structure - verified on TWO spar
+      versions (v0.24.0 = CI pin, and v0.30.0 = latest) x TWO AADL constructs: (a) Data_Model
+      properties (Data_Representation=>Array, Base_Type=>Float, Dimension=>16) and (b) a data
+      implementation with Base_Types::Float subcomponents. Both drop the structure and emit
+      `type vehicle-state = list<u8>`. So REQ-PIX-007's "WIT-typed contracts" can only be OPAQUE bytes
+      with spar's current codegen; jess must NOT hand-write a structured WIT (that violates the
+      derived-from-spar-never-hand-written discipline + breaks the TEST-PIX-023 derivation gate). Filed
+      spar#345 (respectful question/friction; spar HAS a data-plane marshalling feature
+      REQ-CODEGEN-WIT-DATAPLANE-001, so this may be a missing construct rather than a pure gap) with the
+      exact repro + jess impact + the suggested mapping (data-impl subcomponents -> WIT record;
+      Data_Model Array+Float+Dimension -> list<f32>). jess CONSEQUENCE: the byte-exact NavState crossing
+      is proven (TEST-PIX-030) but the TYPED-contract half of REQ-PIX-007 is spar-GATED - the current
+      opaque `list<u8>` WIT is the state until spar#345 lands or the construct is clarified. NOT
+      blocking the on-target path (falcon is #369-gated regardless), but blocks the REQ-PIX-007 refinement.
+    tags: [feature-loop, spar, aadl, wit, codegen, inter-core, navstate, req-pix-007, filed-upstream]
+    fields:
+      detected-by: jess feature-loop (REQ-PIX-007 WIT-typing) - spar v0.24.0 + v0.30.0 both emit list<u8> for structured AADL data (Data_Model + data-impl subcomponents); filed spar#345
+      severity: minor
+      triage-status: filed-upstream
+    links:
+      - type: defect-against
+        target: EXTERNALANCHOR-008
+      - type: traces-to
+        target: REQ-PIX-007

artifacts/phase2-pixhawk.yaml

@@ -1028,8 +1028,11 @@ artifacts:
       Hermetic: committed producer/consumer ELFs (arm-none-eabi, build.sh regenerates; ELF addresses +
       the robot are a matched pair). This is the inter-core IPC foundation the FIRST-FLASH 3-core model
       needs; the MU doorbell datapath (M4->M7 RR0) is separately exercised by the vehicle multinode demo
-      (TEST-PIX-019). NEXT RUNG: WIT-type the NavState record (REQ-PIX-007 / spar codegen) + swap the
-      fixed pattern for relay's real estimator NavState when the M4 estimator lowers on-target.
+      (TEST-PIX-019). NEXT RUNG: WIT-type the NavState record (REQ-PIX-007) - currently spar-GATED
+      (AFD-036/spar#345: spar codegen emits opaque list<u8> for every AADL data type, not a structured
+      record/list<f32>), so the typed-contract half of REQ-PIX-007 waits on spar; the byte-exact
+      crossing (this test) is independent of it. Then swap the fixed pattern for gale's verified k_msgq
+      (gale v0.4.0, DD-023) + relay's real estimator NavState when the M4 estimator lowers on-target.
     tags: [phase-2, inter-core, ipc, navstate, shmem, dual-core, rt1176, byte-exact, on-target, ci-gate, oracle, verification, req-pix-007]
     links:
       - type: verifies

artifacts/suppliers.yaml

@@ -103,3 +103,18 @@ artifacts:
     links:
       - type: traces-to
         target: REQ-001
+
+  - id: EXTERNALANCHOR-008
+    type: external-anchor
+    title: spar (AADL→WIT/analysis) — architecture-model supplier boundary
+    status: accepted
+    description: >
+      pulseengine/spar is the AADL modeling + analysis tool: jess's hardware/pixhawk6x-rt.aadl is the source of truth for the 3-core + peripheral architecture, and `spar codegen --format wit` DERIVES the inter-core WIT contracts from it (REQ-PIX-007 / TEST-PIX-023, the WIT-derivation CI gate). An external supplier; its internal implementation is not traced here. Defects affecting jess's model->WIT derivation (e.g. structured data types) are recorded as ai-found-defects against this boundary.
+    tags: [supplier, spar, aadl, wit, codegen]
+    fields:
+      expected-derived-types: ["ai-found-defect"]
+      received-status: not-received
+      source-of-truth: {"org": "pulseengine", "doc-id": "spar-codegen-wit"}
+    links:
+      - type: traces-to
+        target: REQ-PIX-007