feature: WIT-type the inter-core contract — NavState (16×f32) + ActuatorCmd (4×f32) records (REQ-PIX-007)

[avrabe]

What

Closes REQ-PIX-007's WIT-typed-contract half. The byte-exact NavState crossing was proven last tick (TEST-PIX-030); this adds the typed record so the inter-core ABI reflects the real 64 B payload, not opaque list<u8>.

The spar#345 resolution (honest correction)

The spar maintainer answered spar#345 and split it cleanly:

• The data-implementation record path already works on the CI-pinned spar v0.24.0 (REQ-CODEGEN-WIT-RECORDS-001). My last-tick "spar emits list<u8> for all data" was a modeling error — I bound the port to the bare type (out data port VehicleState) while the subcomponents lived on the implementation (VehicleState.nav).
• The separate Data_Representation=>Array gap was real and the maintainer fixed it upstream (spar PR#346 → list<f32, 16>); jess doesn't need it — the record path is cleaner.

The feature (architecture → spar → WIT)

• hardware/pixhawk6x-rt.aadl: a local data F32 (Data_Size => 4 Bytes, Data_Representation => Float), VehicleState.nav (16 f32 IEKF fields), ActuatorCmd.pwm (4 f32 per-motor); the 4 inter-core ports bound to the implementations.
• wit/ regenerated via spar v0.24.0 → record vehicle-state-nav { qw..baz: f32 } + record actuator-cmd-pwm { m0..m3: f32 }. The TEST-PIX-023 WIT-derivation gate passes (committed wit/ == spar codegen).
• AFD-036 → resolved; TEST-PIX-030 note updated (REQ-PIX-007 now has both crossing + typed contract).

Verification

• rivet validate → PASS
• spar parse + instance → OK
• WIT-derivation gate (regen.sh --check, spar v0.24.0) → OK

Release-watch (same tick)

kiln v0.4.4 (resource_limits, SR-45) + spar v0.31.0 — neither jess-critical; falcon still v1.127 / 14 skips (AFD-035); no inbound.

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