coord: gale v0.5.0 CUT — the 0.5 safety track is verified (partition switch / HM-failsafe / MPU / timer) - #166
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…erified (partition switch / HM-failsafe / MPU / timer) Release-watch: the gale 0.5 safety track (the user-flagged watch item) is now CUT + verified. gale v0.5.0 ships the VERIFIED safety substrate jess's failsafe+partition need: - VER-OS-SWITCH-001: two-level partition switch (verified Switcher x verified MPU; qemu + multi-core Renode demo) -> REQ-PIX-004 / DD-025 ARINC-653. - VER-OS-HM-001: Health-Monitor cross-sensor voting + per-cause failsafe demonstrator -> REQ-PIX-009 F100 failsafe. - VER-OS-ISO-001 (I-ISO MPU isolation) + VER-OS-TIMER-001 (tickless sleep) + VER-OS-SYSCALL-001. - gust-target-gen spar/AADL model SILICON-VALIDATED on STM32F100 (jess's F100 core) + STM32G474. So the safety FSMs move from "0.5-track WATCH item" (last tick) to DELIVERED+verified. Recorded on DD-023 GALE row + REQ-PIX-004 + REQ-PIX-009 + memory. STILL BLOCKED (last-tick finding holds): consuming the FSMs/k_msgq needs the ~9-symbol scheduler seam (k_spin_lock, z_ready_thread, z_reschedule, z_unpend_first_thread, gale_w_msgq_pend/ thread_swap_data/memcpy, arch_thread_return_value_set) - the v0.5.0 release ships only msgq/mutex/ sem .o, not the standalone kernel-seam/FSM objects. jess links the fused gale-nano core (or files the seam ask when it can bind, #369/float-gated). Also (STEP 1): falcon-v1.128 wasm is BYTE-IDENTICAL to v1.127 (54020c5e) - proof-only (MATHF32-P04/ P05 sin/cos bounds) + OCI publishing, no flight-code change -> skips unchanged at 13. synth v0.50.1 is a patch. No inbound. rivet validate PASS. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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…self-verify findings) (#169) Clean-room self-verify (2026-07-24) came back 5/7 CONFIRMED (WIT seams derive from AADL, rivet PASS, REQ-PIX-007 'implemented' + AFD-036 'resolved' both honest, DD-026 records match the real threads, CI gates non-bypassed). Two findings recorded on DD-026: - CAVEAT: the relay/jess/gale 'agreements' (jess#167, gale#223/#225) are all one maintainer (avrabe) across supplier hats - single-actor coordination, not independent sign-off. jess must keep validating claims against the REAL BUILD (per AFD-035), and the mechanical acceptance gates (gust:hal-residual check, falcon-rate consumption run, closed-loop-survives-lowering) are what make it real - not thread consensus. - MELD WATCH v0.42.0: ADR-7 multiply-instantiated + PIC linking, relevant to the per-core fuse; CI pinned v0.41.3; re-verify the reproducibility gate + multi-component fuse when un-floated. (The self-verify also flagged a CI-hygiene gap: #166/#168 main-branch push runs didn't complete - #166 concurrency-cancelled, #168 stuck queued - though both PR-branch runs were verified green before merge. This PR's merge re-triggers a fresh main run to close it.) rivet validate PASS. Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
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Release-watch: the gale 0.5 safety track (the WATCH item you flagged) is now cut + verified.
What gale v0.5.0 delivered (verified)
gust-target-genspar/AADL model silicon-validated on STM32F100 (jess's F100 core!) + STM32G474.So the safety FSMs jess's failsafe+partition need move from "0.5-track WATCH item" (last tick) to delivered+verified. Recorded on the DD-023 GALE row + REQ-PIX-004 + REQ-PIX-009 + memory.
Still blocked (last-tick finding holds)
Consuming the FSMs /
k_msgqneeds the ~9-symbol scheduler seam (k_spin_lock,z_ready_thread,z_reschedule,z_unpend_first_thread,gale_w_msgq_pend/thread_swap_data/memcpy,arch_thread_return_value_set) — the v0.5.0 release ships onlymsgq/mutex/sem.o, not the standalone kernel-seam/FSM objects. jess links the fused gale-nano core (or files the seam ask when it can bind — #369/float-gated).STEP 1 (same tick)
54020c5e) — proof-only (MATHF32-P04/P05 sin/cos bounds) + OCI publishing → skips unchanged at 13.rivet validate→ PASS.🤖 Generated with Claude Code