release-watch: synth v0.51.0 on real fused falcon v1.128 — float gate unchanged (aarch64 release) - #170
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…at gate UNCHANGED (aarch64 release, ARM path untouched) STEP-1 release-watch: synth v0.51.0 shipped. Tested against the REAL fused falcon v1.128 (sha 54020c5e) on the full DD-018 chain (meld 0.39 -> loom 1.2 -> synth --relocatable -t cortex-m7dp), controlled 0.50.0-vs-0.51.0 on identical input: BYTE-IDENTICAL 9-skip set (F32ConvertI64S x3, spill-exhaust x2, no-free-callee, arm-compile-fail x3). v0.51 is an aarch64 backend release (#851) + oracle hardening (#850) - it does not touch the ARM/cortex-m float lowering path, so the unchanged gate is the correct, expected result (no regression, no progress on offer). AFD-035 progression log updated; no upstream issue (v0.51 didn't target the gate). rivet validate PASS. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
…ild-matrix rung) synth v0.51.0 on the same fused+loom falcon v1.128, swept per target ISA: m7dp=9, m7=9, m4f(estimator)=9, m4=30, m3(F100-class)=30. Three reads: (1) F32ConvertI64S=3 on every target = target-independent irreducible float-gate core; (2) M7 + M4-estimator share the same 9-skip VFP floor (no separate estimator pole); (3) soft-float explodes RA pressure 6->27 -> independently confirms F100 runs the small gale VER-OS-HM-001 failsafe FSM, NOT a lowered full falcon (validates DD-025 partitioning + DD-026 decision 4). rivet validate PASS. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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STEP-1 release-watch. synth v0.51.0 shipped (2026-07-23). Tested against the real fused falcon v1.128 (sha
54020c5e) per the AFD-035 "verify against the real build" discipline.Pipeline (full DD-018 chain):
meld 0.39 fuse → loom 1.2 optimize → synth --relocatable -t cortex-m7dp, controlled A/B on the identical fused+loom'd input.Result: synth 0.50.0 and 0.51.0 emit a byte-identical 9-skip set — same functions, same reasons:
func_29/31/42—F32ConvertI64S(i64→f32 conversion, arm backend can't lower) ×3func_36/78— spill-slot pool exhausted ×2func_88— no free callee-saved register ×1func_69/75/172— arm backend compilation-failed ×3Why unchanged is correct: v0.51.0 is an aarch64 backend release (#851 — aarch64 non-param locals + linmem load/store, "runs real WASM modules") + differential-oracle hardening (#850/#853). It does not touch the ARM/cortex-m float lowering path that holds the falcon skips. aarch64 is orthogonal to the RT1176 (M7/M4/M3 — all cortex-m), so no falcon-lane movement was on offer. No regression, no progress, no upstream issue (v0.51 didn't target the gate).
Dominant residual blocker family stays F32ConvertI64S + register-allocation exhaustion. Gate STILL OPEN. AFD-035 progression log updated. (Count note: the 9 here is the loom-optimized full chain; the historical "13" was pre-loom-optimize — loom clears ~4 skippable funcs.)
rivet validate→ PASS.🤖 Generated with Claude Code