chore(release): bump to v0.20.0

[avrabe]

Cuts v0.20.0 — the TSN synthesis track, end to end.

Shipped (5 implemented requirements — a coherent ingest → synthesize → bridge → export story)

Req	What
REQ-INGEST-DBC-FLOWS-001	CAN/DBC message flows as AADL ports + bus-bound connections
REQ-TSN-SYNTH-QBV-BASE-001	802.1Qbv GCL synthesis baseline (exact TAS round-trip oracle)
REQ-TSN-SYNTH-CQF-BASE-001	Standard CQF synthesis baseline (single cycle-time)
REQ-TSN-SYNTH-CQF-BRIDGE-001	AADL SystemInstance → CqfFlow → synthesize_cqf bridge
REQ-TSN-EXPORT-YANG-001	802.1Qcw ieee802-dot1q-sched YANG/NETCONF config export

Version

Workspace 0.19.0 → 0.20.0 (Cargo.toml, Cargo.lock, vscode-spar/package.json).

Scope cut (deliberate, logged)

The 16 requirements still tagged release: v0.20.0 but not yet implemented are bumped to v0.21.0 so the release scope honestly reflects what shipped — 6 planned architecture/solver backlog + 10 proposed (several gated: ARXML behind kill-gate + autosar-data dep, NC-PLP-002 on cyclic panco fixtures, MILP-001 on the TAS-composition soundness experiment). No requirement is dropped. Shipped reqs terminate at implemented per project convention (no release in this repo uses verified).

Pre-tag verification

Clean-room self-verify (independent fresh-context review of the merged scope) → GO: every shipped req is V-closed by a passing verification artifact; prior tags v0.16–v0.19 each carry a genuine success CI run. Two gaps it surfaced were fixed first in #295.

🤖 Generated with Claude Code

[codecov]

Codecov Report

✅ All modified and coverable lines are covered by tests.

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[github-actions]

Rivet verification gate

✅ 20/20 passed

	count
Passed	20
Failed	0
Skipped (no steps)	0

Filter: (and (= type "feature") (or (has-tag "v093") (has-tag "v0100")))

Failed artifacts

(none)

_{Updated automatically by tools/post_verification_comment.py. Source of truth: artifacts/verification.yaml.}