target/riscv: SOCCP support — platform-defined local interrupts and vendor CSR#144
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The default case in riscv_cpu_set_irq hits g_assert_not_reached() for any IRQ number outside the hardcoded set (0-11). The RISC-V privilege spec allows platform-defined local interrupts starting at IRQ 12. SC8480XP SOCCP uses IRQ 21 (RSC) and IRQ 27 (qtimer). Route IRQ >= 12 through riscv_cpu_update_mip() so platforms can use custom local interrupt numbers without hitting the assertion. Signed-off-by: Gary Zancanelli <gzancane@qti.qualcomm.com>
Add vendor_core_disable CSR at 0x7c1 with read_zero/write_ignore semantics. Zephyr firmware on SC8480XP SOCCP accesses this register during init; without it QEMU raises an illegal instruction exception. Signed-off-by: Gary Zancanelli <gzancane@qti.qualcomm.com>
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Adds the RISC-V core support required by the Glymur SC8480XP SOCCP subsystem, rebased onto v11
Main Changes:
Allows local interrupt sources at IRQ index ≥ 12 (platform-defined range) to
be delivered to the RISC-V core, as required by the SOCCP PLIC wiring.
Registers vendor CSR
0x7c1as a read/write no-op so SOCCP firmware thattouches it does not trap with an illegal-instruction exception.