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Fix description rp2350 svd #2845

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Fix description rp2350 svd #2845

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04b35a9
Fix the description of RISC-V's MTIME register
hpcraink Mar 2, 2026
591e1ef
Fix the comments on MTIME in the headers as well
hpcraink Mar 2, 2026
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2 changes: 1 addition & 1 deletion src/rp2350/hardware_regs/RP2350.svd
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Expand Up @@ -76208,7 +76208,7 @@ SPDX-License-Identifier: BSD-3-Clause
<register>
<name>MTIME</name>
<addressOffset>0x000001b0</addressOffset>
<description>Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence.</description>
<description>Read/write access to the low half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence.</description>
<resetValue>0x00000000</resetValue>
<fields>
<field>
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2 changes: 1 addition & 1 deletion src/rp2350/hardware_regs/include/hardware/regs/sio.h
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Expand Up @@ -2132,7 +2132,7 @@
#define SIO_MTIME_CTRL_EN_ACCESS "RW"
// =============================================================================
// Register : SIO_MTIME
// Description : Read/write access to the high half of RISC-V Machine-mode
// Description : Read/write access to the low half of RISC-V Machine-mode
// timer. This register is shared between both cores. If both
// cores write on the same cycle, core 1 takes precedence.
#define SIO_MTIME_OFFSET _u(0x000001b0)
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2 changes: 1 addition & 1 deletion src/rp2350/hardware_structs/include/hardware/structs/sio.h
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Expand Up @@ -249,7 +249,7 @@ typedef struct {
uint32_t _pad3[2];

_REG_(SIO_MTIME_OFFSET) // SIO_MTIME
// Read/write access to the high half of RISC-V Machine-mode timer
// Read/write access to the low half of RISC-V Machine-mode timer
// 0xffffffff [31:0] MTIME (0x00000000)
io_rw_32 mtime;

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2 changes: 1 addition & 1 deletion src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/RP2350.h
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Expand Up @@ -4017,7 +4017,7 @@ typedef struct { /*!< SIO Structure
interrupts are routed to normal system-level interrupt
lines as well as to the MIP.MTIP inputs on the RISC-V cores. */
__IM uint32_t RESERVED3[2];
__IOM uint32_t MTIME; /*!< Read/write access to the high half of RISC-V Machine-mode timer.
__IOM uint32_t MTIME; /*!< Read/write access to the low half of RISC-V Machine-mode timer.
This register is shared between both cores. If both cores
write on the same cycle, core 1 takes precedence. */
__IOM uint32_t MTIMEH; /*!< Read/write access to the high half of RISC-V Machine-mode timer.
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