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CI broke because the big-endian targets got dropped out of Tier 2. #15 fixes this. |
adamgreig
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Feb 3, 2026
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LGTM. Can you rebase onto #15 to fix CI? |
This involves different registers to those used when a processor is running in AArch32 mode. These changes have been tested inside the Lauterbach TRACE32 AArch64 ISA simulator, which supports Arm DCC. This was developed by Ferrous Systems on behalf of Arm. Arm is the owner of these changes.
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Rebased - I'll merge when CI passes. |
Contributor
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Wow, speedy. That was about 30 seconds! |
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This PR adds support for communicating over the Arm Debug Communication Channel (DCC) from a processor running in AArch64 mode. This involves different registers to those used when a processor is running in AArch32 mode.
These changes have been tested inside the Lauterbach TRACE32 AArch64 ISA simulator, which supports Arm DCC.
This PR was developed by Ferrous Systems on behalf of Arm. Arm is the owner of these changes.