Add unchecked_shl and unchecked_shr for SIMD integers#488
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GrigoryEvko wants to merge 1 commit intorust-lang:masterfrom
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Add unchecked_shl and unchecked_shr for SIMD integers#488GrigoryEvko wants to merge 1 commit intorust-lang:masterfrom
GrigoryEvko wants to merge 1 commit intorust-lang:masterfrom
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Adds unchecked shift operations to SimdInt and SimdUint traits. These skip the masking that regular shifts perform, providing optimization opportunities when the shift amount is known to be valid. Regular shifts mask: (value << rhs) where rhs &= (BITS-1) Unchecked shifts: direct simd_shl/simd_shr without masking Safety: Caller must ensure shift amount < BITS for all lanes.
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Perhaps use test_helpers::test_binary_elementwise but apply a bitmask/clamp to the rhs argument to ensure it's always less than the number of bits.
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Description:
Partially addresses #481 by adding unchecked shift operations to
SimdIntandSimdUinttraits.Changes
Adds
unchecked_shlandunchecked_shrmethods that skip the shift amount masking performed by regular shiftoperators. These provide optimization opportunities when the shift amount is known to be valid.
Regular shifts:
value << rhs // Masks: rhs &= (BITS - 1)Unchecked shifts:
unsafe { value.unchecked_shl(rhs) } // Direct simd_shl without maskingScope
This PR implements only shift operations, not arithmetic operations (add/sub/mul).
Rationale: SIMD arithmetic operations use the same LLVM intrinsics as regular operators (simd_add, simd_sub,
simd_mul) and provide no optimization benefit. LLVM does not currently expose nsw/nuw (no signed/unsigned
wrap) variants for SIMD vectors. In contrast, shift operations can skip the masking instruction, providing
measurable performance improvement.
Safety
Caller must ensure rhs < T::BITS for all lanes. Violating this results in undefined behavior.
Testing
Tests included for:
Closes #481
Related: rust-lang/libs-team#662