Support GPR pair in RISC-V inline assembly

[taiki-e]

This supports RISC-V even-odd GPR pair as reg_pair class under asm_experimental_reg feature (#133416).

Both LLVM (20+) and GCC support this as R constraint, and this is useful for using AMOCAS.D on RV32 and AMOCAS.Q on RV64 instructions (currently, we need to split the value and pass it by specifying the specific register name).

Note: For now, this only implements register class and support for explicitly specifying register names is not implemented. (What name should we choose?)

Architecture	Register class	Target feature	Allowed types
RISC-V32	reg_pair		i64
RISC-V64	reg_pair		i128

Refs:

• Inline Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs riscv-non-isa/riscv-c-api-doc#92
• [RISCV] Inline Assembly Support for GPR Pairs ('R') llvm/llvm-project#112983

r? @Amanieu

@rustbot label +A-inline-assembly +O-riscv

[rustbot]

Some changes occurred in compiler/rustc_codegen_gcc

cc @antoyo, @GuillaumeGomez

[rustbot]

This PR was rebased onto a different main commit. Here's a range-diff highlighting what actually changed.

Rebasing is a normal part of keeping PRs up to date, so no action is needed—this note is just to help reviewers.

[Amanieu]

I would expect this to come with a format modifier which allows you to get the name of the second register of the pair.

[taiki-e]

Indeed, it would significantly limit its uses without that.

@rustbot author

[rust-bors]

☔ The latest upstream changes (presumably #152825) made this pull request unmergeable. Please resolve the merge conflicts.