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draft: arch: Add Hexagon HVX instructions #1999
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r? @folkertdev rustbot has assigned @folkertdev. Use |
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cc @folkertdev I'm still working out how to get the CI to execute this, I should be able to make it work with |
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Yeah I figured that would be a bit of a challenge, so more efficient to do that in parallel. |
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General note: this looks largely machine-generated? We already have stdarch-gen-loongarch and stdarch-gen-arm, so it's possible to check that in.
Ok, will add the generation script here too. |
crates/core_arch/src/hexagon/hvx.rs
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| #[inline] | ||
| #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] | ||
| #[unstable(feature = "stdarch_hexagon", issue = "none")] |
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For most targets we like adding a test that the intrinsic does in fact produce the expected instruction, e.g.
// avx512bw
#[cfg_attr(test, assert_instr(vpabsw))]
// wasm
#[cfg_attr(test, assert_instr(v128.load8x8_s))]
especially if you are machine-generating these that should hopefully be straightforward.
crates/core_arch/src/hexagon/hvx.rs
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| /// Execution Slots: SLOT0123 | ||
| #[inline] | ||
| #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] | ||
| #[unstable(feature = "stdarch_hexagon", issue = "none")] |
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before we merge this you can create a tracking issue in the main repo, see e.g. rust-lang/rust#117427
crates/core_arch/src/hexagon/hvx.rs
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| #[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] | ||
| #[unstable(feature = "stdarch_hexagon", issue = "none")] | ||
| pub unsafe fn q6_v_vxor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { | ||
| vxor(vu, vv) |
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it's a bit hard to deduce from the names, but I'm assuming this corresponds to simd_xor
https://doc.rust-lang.org/nightly/std/intrinsics/simd/fn.simd_xor.html
We generally prefer using functions from crate::intrinsics::simd (starting with crate is deliberate, using core:: can cause trouble when bootstrapping). It's much easier for us to then know what a function does, and as a bonus Miri will be able to run the intrinsics too.
When using intrinsics::simd it is even more important to check that these functions emit the right instruction. Sometimes additional optimizations are needed in LLVM to make that work.
I think it's fine to do this gradually, but for some of the simpler operations it's probably possible to do it from the start.
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for some of the simpler operations it's probably possible to do it from the start.
Sure - can do!
Ah - okay, I see that these are different from what I've implemented. I have a python script that takes a C/C++ toolchain header file as a source-of-truth. So @folkertdev should I implement that instead as a crate that parses a yaml file? |
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The input is up to you, We would prefer having rust over python though, hopefully that is straightforward to port? |
It is, yeah.
Sorry, not sure if I follow. Add comments in the C header file used as an input? Or ... ? |
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Taking Maybe this was unclear, but currently the workflow is that we don't manually update the generated rust code, but instead modify the inputs to the generator and re-run it. That is convenient when new instructions are added, and it is usually simpler to edit the input than the output. Anyhow, none of that is official, that's just what we have. So if there are good reasons to deviate from it that is something we can discuss. |
Ah okay I gotcha now. So my plan was to just include a hardcoded list in the script/rust program of the intrinsics that do map to the architecture-independent ones and the exceptions get lowered to the architecture-specific ones. |
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Cool, that should work |
Update tracking issue from "none" to "151523"
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doing a quick close/open here to see what CI says now that the features are available |
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hmm is there some issue with hexagon in |
This I have been noodling over the design of this PR and have several local changes. None of them were intended to address the |
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Weird. We're using latest nightly here, maybe something was not synchronized? |
- Regenerate hvx.rs with dual 64b/128b vector mode support - Generator: add compound overrides for pred/vec type conversions - Generator: use .128B LLVM intrinsic suffix for 128-byte mode - Generator: use #[inline(always)] for intrinsic wrappers - Add gaussian 3x3 blur HVX example
Yeah, it's not obvious to me yet. This was fixed a while ago (rust-lang/compiler-builtins#682). I'll need to spend some time trying to reproduce it and maybe something just needs to update an explicit compiler-builtins dependency to a newer release. |
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Oh, yes, it's building |
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Note that we don't use crates.io c-b anymore, it should only ever be coming via the submodule which is actively updated. Think this will still technically show as 0.1.160 though. |
Note: this depends on #151500
Tracking issue #151523