Verilisp

Verilisp is a Common Lisp macro system that generates Verilog HDL code, turning Common Lisp into a frontend for Verilog.

Originally based on code from Google Code (no longer maintained), this fork has been substantially rewritten with a new AST-based compiler architecture:

• AST representation: Verilog constructs are represented as keyword-tagged lists (:module, :wire, :always, etc.) generated by CL macros
• 2-pass compilation: Pass 1 expands CL macros to produce AST nodes; Pass 2 emits Verilog text from the AST
• CL package-based symbol resolution: Uses the Common Lisp package system instead of name mangling
• SystemVerilog output: Optional SV target with logic, always_ff, always_comb support
• Static analysis: Dead code detection, undriven wire detection, loop detection, width mismatch warnings

Usage

./verilisp input.hvl              # Verilog output to stdout
./verilisp input.hvl -o out.v     # Verilog output to file
./verilisp --sv input.hvl         # SystemVerilog output
./verilisp -tn                    # Run test suite

Requires CLISP with -modern mode (case-sensitive).

Operators

• Non-blocking assignment: <- (e.g., (<- q d))
• Less than or equal: <=, %<=, or =<

License

This project is licensed under the MIT License. See LICENSE for details.

Due to the substantial architectural changes from the original codebase (introduction of AST-based compilation, package-based symbol resolution, and a complete rewrite of the core evaluation pipeline), this fork is released under the MIT License.