Note: This repository only contains the src code files. Workspace of Xilinx Vivado 2023.2. A set of 32 Registers (32-bit wide) according to RISC-V architecture. This RegisterSet can be ScanTestable using a TAP controller.
Tool: Xilinx Vivado 2023.2
HDL: VHDL
Simulation done.
DRC check done.
Synthesis done.
Implementation done.
Bit-stream not performed.
16 state FSM
Instruction Register cell
Data Register cell (scan chain-cell)
BYPASS operation
Scan chain operation
SAMPLE operation
PRELOAD operation
