RISC-V Multicycle Processor

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This repository contains the Verilog HDL implementation of a simple RISC-V Multicycle processor.
For detailed information on the RISC-V instruction set, please refer to the official RISC-V Instruction Set Manual, available in the docs directory (originally from https://riscv.org)

Features

• RISC-V RV32I Instruction Set: Implements a subset of the RV32I instruction set that can be used to write simple programs involving simple arithmetic and logical operations, memory access and branching.
• Multicycle Design: All instructions are broken down into multiple microoperations and executed over multiple cycles, sharing functional units.
• Nonarchitectural registers: To pass on data from one cycle to the next, intermediate values are temporarily stored in nonarchitectural registers.
• FSM-driven control unit: A finite state machine (FSM) tracks the current execution cycle for each instruction, where each state of the FSM corresponds to a particular microoperation and consequently a unique combination of control signals.

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Getting started

Prerequisites

A Verilog simulator is required to test this design. Icarus Verilog (iverilog) and GTKWave (gtkwave) were used in the development of this project.

    sudo apt-get install iverilog gtkwave # For Debian/Ubuntu

To run the program:

    iverilog -o out components/*.v control/*.v datapath/*.v nonarchitectural/*.v Multicycle.v Multicycle_tb.v # generates output file
    vvp out # runs output file
    gtkwave Multicycle.vcd # opens GTKWave software to view waveforms

References

[1] Digital Design and Computer Architecture RISC-V Edition by Sarah Harris, David Harris