This repository contains the source files of the P4 & Verilog NetFPGA SUME implementation of the s-PERC switch. This repo is intended to be a drop-in project for the P4-NetFPGA-live repo.

Repository info:

• src/ - contains the P4 source files
• externs/ - contains the Verilog extern implementations
• testdata/ - contains some basic regression tests for the s-PERC switch
• sw/division - contains software to generate table entries for division tables
• sw/hw_test_tool - contains simple python-based s-PERC endpoints for testing basic functionality
• simple_sume_switch/ - contains NetFPGA specific source files