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Fix indexing into one bit of a spice bus
…ssue with verilog reads
…ill need to fix tests, but will wait until after merge
Implement top_module for all SystemVerilogTargets
Fix minor bugs in Vivado TCL generation
Release 3.0.9
…mverilog, but I broke functionality for spice. Have a lingering TODO to force a wave dump on certain nodes when global waveform dumping is turned off
…into combine_branches
Initial clocks to zero
Insert flags before other command options
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