Old Run Instructions

This is the old version of this page, but I'm a bit paranoid about deleting it because it's a good record of the old mGenero stuff. You probably want the new page here: Modeling a Circuit.

Install

See instructions on the readme here

Set up circuit for testing

First, you need a netlist for the circuit you plan to characterize. The first step is to create a circuit schematic that includes the typical load for the circuit. For an amplifier, you might create a new schematic that has an instance of the amp you want, plus a capacitor/resistor network attached to the output, and then input/output pins connected to the input/outputs you want to model. Typically, this “wrapped” version would have the same exact pinout as the instance, and the only difference is the extra load on the output.

Next, set up an ADEL window for that schematic (which includes an instance of the circuit plus load). This is where you include any global variable values. You MUST also set the model libraries under setup -> model libraries. It’s also best to turn off saved nodes with Results -> save all... -> check “None” for “Select Signals to Save” (the tool will manually add the necessary saves; you can add more saves here if you plan to manually debug the waveforms, but the psf file size will grow and the python library can’t handle that very well). Then export the netlist with simulation -> netlist -> create. Make a note of the location of the exported netlist; you will need it for the config file (you can also move it somewhere convenient, but then you will have to move it again every time you modify the circuit).

Set up config file

You must create a configuration file that is specific to the circuit you want to model. See detailed instructions about the config file here.

Other peripheral files

• Netlist/description for circuit (spice or verilog), which you probably exported from Virtouso
• Simulator setup file
  • Has information about running the simulator
  • Typically one of these files can be used across all circuits
  • Examples for spectre, ngspice, iverilog, ncsim with mLingua includes
  • The available commands mostly correspond to the fault.Target options, documented here for spice and here for Verilog
• mGenero config file
  • This tells the tool how to create all the necessary files to run mGenero, which will insert the measured parameters into the functional model template
  • This file also sets the mGenero directory, which is where the model will be built
  • Theoretically this file should not depend on the specific circuit and can be taken directly from the template library, but right now you may have to make some manual tweaks
  • Example here, but it's a bit outdated - I don't have one right now that can be shared publicly
• Templatized Verilog model
  • Hand-written Verilog model with annotations to insert extracted data
  • Should be part of the template library. Right now I don't have them organized anywhere; I've been pulling from the original mGenero templates here but I sometimes need to make modifications

Running

You can run the tool from any directory, and it will create its build folder (called checkpoint_folder/) in that directory. It will also create a directory called plots/ in that directory for plots about circuit behavior.

Finally, you can run the tool:

python -m fixture.run path/to/config.yaml

The last thing the program outputs is the set of parameters it extracted. If mgenero is also set up, then those parameters are also written to an output file params.yaml in the mgenero output folder. The Verilog model can be created my navigating to that mgenero output folder and running

python generate.py

The default name for the resulting verilog model is final.sv.