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Description

Add raw data and metadata for the CS 537 Fall 2021 Midterm exam.

Changes

  • Add exam directory /home/qi/system-intelligence-benchmark/benchmarks/courseexam_bench/data/raw/cs537_fall_2021_midterm.
  • Add solutions file 21-fall-mid-solutions.pdf to the exam directory.
  • Add exam metadata for Exam title "CS 537 Fall 2021 Midterm" and Exam ID cs537_fall_2021_midterm. Reference files: none.

Testing

Prepared and validated the new exam data by running: python3 courseexam/prepare.py

Checklist

  • Tests pass locally
  • Code follows project style guidelines
  • Documentation updated (if needed)

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This one looks good to me

@qimcis qimcis force-pushed the cs537-fall-2021-midterm branch from ac74c7a to c7daba0 Compare January 26, 2026 15:39
@qimcis qimcis force-pushed the cs537-fall-2021-midterm branch from c7daba0 to d264616 Compare January 26, 2026 16:34
@qimcis qimcis marked this pull request as ready for review January 27, 2026 04:49
@xuafeng xuafeng requested review from Copilot and tareknaser January 27, 2026 05:22
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Pull request overview

This PR adds the CS 537 Fall 2021 Midterm exam data to the courseexam benchmark. The exam consists of 32 multiple-choice questions covering operating systems topics including scheduling, memory management, paging, and TLB operations.

Changes:

  • Added exam.md with metadata and 32 multiple-choice questions for CS 537 Fall 2021 Midterm
  • Added 21-fall-mid-solutions.pdf containing the exam solutions

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Comment on lines +314 to +612
17. Minux uses kernel mode, user mode, and a new mode called “supervisor” mode. When a user
program runs in “supervisor” mode, it is still restricted (like user mode), but can do the following: change
the length of the timer interrupt interval, including turning it off. Overall, would you say that supervisor
mode (choose one):


```json
{
"problem_id": "17",
"points": 3,
"type": "ExactMatch",
"tags": ["minux"],
"choices": ["Helps ensure streamlined round-robin scheduling","Ensures more efficient, application-aware timing interrupts","Better integrates scheduling and virtual memory mechanisms","Limits the OS’s ability to retain control of the machine if user code runs in supervisor mode","None of the above"],
"answer": "C"
}
```

---

## Question 18 [3 point(s)]

18. Minux employs a (two-level) multi-level page table. Assume a 32-bit virtual address space, and 4 KB
pages. Also assume each page table entry (PTE) is 4 bytes in size. How many PTEs fit onto one page?

```json
{
"problem_id": "18",
"points": 3,
"type": "ExactMatch",
"tags": ["minux"],
"choices": ["1","32","1024","4096","None of the above"],
"answer": "C"
}
```

---

## Question 19 [3 point(s)]

19. Assuming a two-level multi-level page table (32-bit virtual addresses, 4KB pages, 4-byte PTE size),
what is the minimum number of valid virtual pages in an address space such that the multi-level page
table becomes its maximum size?

```json
{
"problem_id": "19",
"points": 3,
"type": "ExactMatch",
"tags": ["minux"],
"choices": ["512","1024","2048","4096","None of the above"],
"answer": "B"
}
```

---

## Question 20 [3 point(s)]

20. Assuming a two-level multi-level page table (32-bit virtual addresses, 4KB pages, 4-byte PTE size),
what is the minimum number of pages needed for the multi-level page table (including the page
directory) when there are 1025 contiguous valid pages somewhere in the virtual address space?

```json
{
"problem_id": "20",
"points": 3,
"type": "ExactMatch",
"tags": ["minux"],
"choices": ["3","4","5","1025","None of the above"],
"answer": "A"
}
```

---

## Question 21 [3 point(s)]

21. TLBs make hardware more complex, so Minux definitely uses one. The best description of what a
TLB is as follows (choose one):

```json
{
"problem_id": "21",
"points": 3,
"type": "ExactMatch",
"tags": ["minux-tlb"],
"choices": ["A memory to store page table entries","A collection of base/bounds pairs to help segmentation work quickly","An OS component to speed up translation","A hardware feature that ensures fair use of memory","An address-translation cache"],
"answer": "E"
}
```

---

## Question 22 [3 point(s)]

22. Assume the TLB, which has just four entries, has the following contents (numbers in the TLB are all
decimal, and entries are all valid):

VPN 0 -> PFN 1

VPN 1 -> PFN 100

VPN 2 -> PFN 101

VPN 3 -> PFN 102

Assume this system has a 14-bit virtual address, and 4-KB pages. What virtual address will access the
physical address 50 (decimal)?

```json
{
"problem_id": "22",
"points": 3,
"type": "ExactMatch",
"tags": ["minux-tlb"],
"choices": ["0x0032","0x1023","0x3012","0x3132","None of the above"],
"answer": "E"
}
```

---

## Question 23 [3 point(s)]

23. When running on Minux, calculate the hit rate of the TLB assuming a process has 4-KB pages, and
accesses every 128th byte on a series of pages. Assume the TLB begins empty, and ignore code
accesses and just focus on this “strided” data access pattern.

```json
{
"problem_id": "23",
"points": 3,
"type": "ExactMatch",
"tags": ["minux-tlb"],
"choices": ["Just about 99%","Just about 88%","Just about 50%","Just about 17%","None of the above"],
"answer": "D"
}
```

---

## Question 24 [3 point(s)]

24. The Minux scheduler uses a new scheduler called “highest process ID first” (i.e., the job with
the highest PID always runs, and to completion). Assume job PID=1 arrives at time T=0, with length 10;
PID=2 arrives at T=2, length=6; PID=3 arrives at T=4, with length 4. What is the average response time
of this approach in this example?

```json
{
"problem_id": "24",
"points": 3,
"type": "ExactMatch",
"tags": ["minux-scheduling"],
"choices": ["1","2","3","4","None of the above"],
"answer": "E"
}
```

---

## Question 25 [3 point(s)]

25. To reduce the size of page tables, ZOS combines the idea of base/bounds and paging. A virtual
address space is still chopped into pages. The page table is pointed to by the base register, and the
bounds register holds the “size” of the page table (really, the max VPN that is valid, plus one). This
approach (choose one):

```json
{
"problem_id": "25",
"points": 3,
"type": "ExactMatch",
"tags": ["zos-base-bounds"],
"choices": ["Enables fast translation with only two extra memory references to fetch a PTE","Enables a compact page table, if you use the virtual address space carefully","Is always smaller than a linear page table","Supports a sparse address space while still also minimizing page table memory usage","None of the above"],
"answer": "D"
}
```

---

## Question 26 [3 point(s)]

26. ZOS, as mentioned above (Question 25), combines base/bounds and paging. Assume the following:
a 32-bit address space with 1-KB pages. Assume each page table entry (PTE) is 4 bytes. Assume there
are 100 processes in the system. If each process uses only one virtual page, what is the worst-case
total size of all of these page tables?

```json
{
"problem_id": "26",
"points": 3,
"type": "ExactMatch",
"tags": ["zos-base-bounds"],
"choices": ["16 MB","160 MB","1600 MB","16 GB","None of the above"],
"answer": "E"
}
```

---

## Question 27 [3 point(s)]

27. ZOS uses a new type of scheduler called a proportional-share scheduler. This scheduler makes sure
each process gets a certain amount of CPU time, based on how many “tickets” it has. For example, if
process A has 2 tickets, and process B has 1, A should get twice as much CPU time as B. Note that a
process cannot change how many tickets it has, and all jobs only use the CPU (there is no I/O in this
example). Which of the following traces (which each show which job was scheduled at each quantum
over time) does not show the behavior of a proportional-share scheduler? 


```json
{
"problem_id": "27",
"points": 3,
"type": "ExactMatch",
"tags": ["zos-scheduling"],
"choices": ["AABAABAABAABAA","ABABABABABAB","AAAAAAAAAABBBBB","ABBBABBBABBBABBB","None of the above (they all could be traces from a proportional share scheduler)"],
"answer": "E"
}
```

---

## Question 28 [3 point(s)]

28. ZOS uses a new mechanism instead of timer interrupts. Instead of interrupting the CPU every so
many milliseconds, the ZOS hardware is programmed to interrupt the CPU after every N TLB misses.
How creative! As compared to the timer, this approach (choose one):

```json
{
"problem_id": "28",
"points": 3,
"type": "ExactMatch",
"tags": ["zos-tlb-miss"],
"choices": ["Is equally effective","Is faster to program","Is risky","Requires less memory","Requires virtual memory support"],
"answer": "C"
}
```

---

## Question 29 [3 point(s)]

29. A later version of ZOS uses a different, clever approach to sharing the TLB among active processes.
Assume the hardware does not have an address space identifier (or process identifier) field in the TLB.
Instead of flushing the TLB when switching between processes, ZOS ensures that each process in the
system uses different (unique) VPNs as compare to any other process. Which of the following is not true
about this approach:

```json
{
"problem_id": "29",
"points": 3,
"type": "ExactMatch",
"tags": ["zos-tlb-sharing"],
"choices": ["Allows for fully flexible use of the virtual address space by each process","Allows for faster context switching (as compared to the TLB flushing approach)","Allows for fully flexible use of physical memory","Allows sharing of code pages between processes","None of the above (all are true)"],
"answer": "E"
}
```

---

## Question 30 [3 point(s)]

30. ZOS also later added support for “large” pages, a new and clever idea. Assume that in a given
system, regular page size is usually 1 KB, and large pages are 1 MB. When possible, the OS uses large
pages instead of a bunch of smaller ones (e.g., when there is a contiguous, aligned portion of the virtual
address space in use). Why is using large pages a good idea?

```json
{
"problem_id": "30",
"points": 3,
"type": "ExactMatch",
"tags": ["zos-large-pages"],
"choices": ["They reduce system complexity","They speed up trap handling","They can increase TLB hit rates","They make physical memory allocation easier","None of the above"],
"answer": "C"
}
```

---

## Question 31 [3 point(s)]

31. ZOS also added special hardware, in the form of general-purpose registers that only the kernel can
use. Indeed, all kernel code has been written to only use these registers, not the regular (user-level)
general purpose ones. Why might these registers for the kernel be a good idea?

```json
{
"problem_id": "31",
"points": 3,
"type": "ExactMatch",
"tags": ["zos-kernel"],
"choices": ["Faster trapping into and returning from the kernel","Kernel code now easier to compile","Reduces need for context switching between processes","Now, no way to harm user-level register contents while in kernel code","None of the above"],
"answer": "A"
}
```

---

## Question 32 [3 point(s)]

32. Zinus also had this last question for you: which is true about operating systems?
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Questions 17-32 have redundant question numbers at the start of the question text (e.g., "17. Minux uses...", "18. Minux employs..."). Questions 1-16 do not have this prefix. For consistency, the question numbers should be removed from the question text since they are already specified in the section heading.

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## Question 13 [3 point(s)]

DOS uses paging. Before talking about how randomness was used, let’s do a simple questions to
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Grammatical error: "simple questions" should be "simple question" (singular form).

Suggested change
DOS uses paging. Before talking about how randomness was used, let’s do a simple questions to
DOS uses paging. Before talking about how randomness was used, let’s do a simple question to

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{
"exam_id": "cs537_fall_2021_midterm",
"test_paper_name": "CS 537 Fall 2021 Midterm",
"course": "CS 537",
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The course field should be "Operating Systems" to match the CS 537 Fall 2021 Final exam (cs537_fall_2021_final/exam.md line 7), which is from the same course at the same institution. Both exams should use a consistent course name.

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I only reviewed the first third of the questions. The answers don’t match the reference PDF. Please double-check before requesting another review

17. Minux uses kernel mode, user mode, and a new mode called “supervisor” mode. When a user
program runs in “supervisor” mode, it is still restricted (like user mode), but can do the following: change
the length of the timer interrupt interval, including turning it off. Overall, would you say that supervisor
mode (choose one):

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Not sure what the character is

Suggested change
mode (choose one):
mode (choose one):

Comment on lines +410 to +413
VPN 0 -> PFN 1

VPN 1 -> PFN 100

VPN 2 -> PFN 101

VPN 3 -> PFN 102

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Also here and in other places in the same file

Suggested change
VPN 0 -> PFN 1
VPN 1 -> PFN 100
VPN 2 -> PFN 101
VPN 3 -> PFN 102
VPN 0 -> PFN 1
VPN 1 -> PFN 100
VPN 2 -> PFN 101
VPN 3 -> PFN 102

Comment on lines +106 to +115
```json
{
"problem_id": "6",
"points": 3,
"type": "ExactMatch",
"tags": ["memory-management"],
"choices": ["1000","1023","1024","It depends on the base register","It depends on the bounds register"],
"answer": "E"
}
```
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Answer doesn't match the exam reference solution

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image

Comment on lines +10 to +11
"score_total": 100,
"num_questions": 32
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Not sure how you assigned a specific score for each question. The exam PDF doesn't seem to specify that. Did I miss anything?

Comment on lines +147 to +155
```json
{
"problem_id": "8",
"points": 3,
"type": "ExactMatch",
"tags": ["memory-management"],
"choices": ["Provides strong process isolation","Makes programs run slowly","Allows multiple processes to be active in the system","Affects the type of CPU scheduling policy you can implement","Helps realize a sparse virtual address space"],
"answer": "A"
}
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Answer doesn't match reference solution

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image

Comment on lines +202 to +211
```json
{
"problem_id": "11",
"points": 3,
"type": "ExactMatch",
"tags": ["dos-scheduling"],
"choices": ["45 ms","50 ms","60 ms","120 ms","None of the above"],
"answer": "C"
}
```
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Answer doesn't match reference solution

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image

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3 participants