schedule: zephyr_dma_domain: Add support for shared IRQs#7923
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Quick read through, LGTM, does this need any west update ?
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No west updates needed |
dbaluta
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lyakh
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In the case of DMA channels using the same IRQ line the same interrupt handler with different data is registered multiple times for the same interrupt. This approach works perfectly fine when using the IRQ_STEER IP since the way its driver works is it allows registering multiple handlers+data for the same INTID. When switching to ARM64, this approach no longer works since the last irq_handler/irq_data pair will overwrite the previous one for the same INTID. Because of this, the IRQ bit from the DMA channel may not get cleared when multiple pipeline tasks are scheduled. This reasoning applies to the ARM64 architecture with GICv3 interrupt controller. To overcome this, the Zephyr DMA domain now holds a list of channels using the same IRQ. When the DMA IRQ gets triggered, the handler will iterate through the list of channels using the same IRQ and clear the interrupt. Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
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FYI: currently waiting on #7976 before I can test the changes from this PR. Hopefully that PR will fix the annoying crashes during stress testing. |
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@LaurentiuM1234 Yes, this got through one round of internal CI. Looks good to me. Just take it out of Draft state. |
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@juimonen any comments ? |
No, fine by me. I see this is IMX only. |
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In the case of DMA channels using the same IRQ line the same interrupt handler with different data is
registered multiple times for the same interrupt.
This approach works perfectly fine when using the IRQ_STEER IP since the way its driver works is it allows registering multiple handlers+data for the same INTID.
When switching to ARM64, this approach no longer works since the last irq_handler/irq_data pair will overwrite the previous one for the same INTID. Because of this, the IRQ bit from the DMA channel may not get cleared when multiple pipeline tasks are scheduled. This reasoning applies to the ARM64 architecture with GICv3 interrupt controller.
To overcome this, the Zephyr DMA domain now holds a list of channels using the same IRQ. When the DMA IRQ gets triggered, the handler will iterate through the list of channels using the same IRQ and clear the interrupt.
This PR still requires more testing. For now, it has only been tested on ARM64-based i.MX93 and i.MX8QM and works fine for simple audio cases (i.e: simple playback, simple capture, simple playback with pause/resume)