GitHub - tiffcmw/vpu-accelerator: Hand-written SystemVerilog SIMD core (Fall 2025) followed by an Allo DSL/HLS redesign adding INT8 GEMM, ReLU, and fusion kernels (Spring 2026), targeting the Nexys A7. · GitHub

Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
vpu-allo		vpu-allo
vpu-rtl		vpu-rtl
.gitignore		.gitignore

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Hand-written SystemVerilog SIMD core (Fall 2025) followed by an Allo DSL/HLS redesign adding INT8 GEMM, ReLU, and fusion kernels (Spring 2026), targeting the Nexys A7.

fpga hardware-accelerator hls systemverilog vector-processor vitis-hls

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