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hitsz
Here are 22 public repositories matching this topic...
Verilog miniRV/RISC-V style CPU course project featuring single-cycle and five-stage pipeline designs with hazard handling.
cpu pipeline verilog computer-architecture risc-v digital-design computer-organization cpu-design hitsz
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Apr 27, 2026 - Verilog
An automated line-following car project for the 2022 AUTO1001 course at HITSZ.
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Jul 23, 2025 - C++
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