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Apr 10, 2025 - Python
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llm-based
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Leveraging the powerful cross-lingual understanding capabilities of LLMs to obtain sentence representations, eliminate language-specific features from these representations, and thereby enhance their semantic characteristics.
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May 4, 2026
Reproduction of the HiVeGen (Hierarchical LLM-based Verilog Generation) pipeline from the paper "HiVeGen – Hierarchical LLM-based Verilog Generation for Scalable Chip Design" (arXiv:2412.05393).
llvm verilog systemverilog hardware-designs hdl verilog-hdl hierachical verilog-code hierachical-structure llm-based hivegen hierarchical-hardware-design demo-paper-implementation paper-demo hivegen-demo
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Nov 18, 2025 - SystemVerilog
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