A parameterized multi-cycle Harvard architecture processor designed from the ground up in Verilog. Developed using a complete RTL design workflow including simulation, linting, synthesis, Sky130 technology mapping, area estimation, static timing analysis, cocotb self-checking testbenches and post synthesis GLS 🖥️.
computer-architecture instruction-set-architecture microarchitecture computer-organization performance-modeling turing-complete static-timing-analysis harvard-architecture computer-design rtl-synthesis amdahls-law self-checking-testbenches
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Updated
Aug 7, 2026 - Verilog