implementation of the Serial Peripheral Interface protocol with single port RAM in verilog
-
Updated
Aug 5, 2025 - Verilog
implementation of the Serial Peripheral Interface protocol with single port RAM in verilog
Single port BRAM module for FPGA. VHDL and Verilog versions.
Single-port RAM implemented in Verilog with synchronous read/write and parameterized depth.
Add a description, image, and links to the single-port-ram topic page so that developers can more easily learn about it.
To associate your repository with the single-port-ram topic, visit your repo's landing page and select "manage topics."