Fix: Specialized Linear Layout for Decoupling Capacitors (#15)#32
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Fix: Specialized Linear Layout for Decoupling Capacitors (#15)#32buildingvibes wants to merge 2 commits intotscircuit:mainfrom
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Resolves tscircuit#15 by adding specialized linear layout for decoupling capacitors to create clean, professional-looking schematics. **Changes:** 1. **Enhanced net metadata inference** - Added automatic detection of ground and voltage source nets based on naming conventions (GND, V3_3, VCC, etc.) in `getInputProblemFromCircuitJsonSchematic.ts` 2. **Added rotation constraints** - 2-pin components now have rotation restricted to 0/180 degrees to enable decoupling capacitor identification 3. **Improved decoupling cap detection** - Enhanced `IdentifyDecouplingCapsSolver` to follow strong pin connections when determining net connectivity, enabling detection of caps connected through chip pins 4. **Linear layout for decoupling caps** - Added `createLinearDecouplingCapLayout()` in `SingleInnerPartitionPackingSolver` that arranges decoupling capacitors in clean horizontal rows with uniform spacing **Results:** - RP2040 circuit test now passes with 0 overlaps (previously 4) - Decoupling capacitors arranged in organized linear layouts - Two separate groups for different voltage rails (V3_3 and V1_1) - Consistent 0.2mm spacing between capacitors Fixes tscircuit#15 /attempt tscircuit#15
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The test failure was caused by @tscircuit/schematic-viewer trying to import a non-existent export (convertCircuitJsonToSchematicSimulationSvg) from circuit-to-svg during module evaluation. This caused all tests to fail with a SyntaxError, even though the SchematicViewer component was not actually being used by the failing tests. Changes: - Lazy load SchematicViewer using React.lazy() to defer loading until needed - Wrap SchematicViewer usage in Suspense boundary with loading fallback - Update @tscircuit/schematic-viewer from 2.0.26 to 2.0.56 This prevents the problematic import from being evaluated during test runs where SchematicViewer is not used, fixing the test suite while maintaining full functionality for the circuit viewer tab.
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Summary
Implements specialized linear layout for decoupling capacitor partitions, resolving the messy irregular patterns that were causing component overlaps.
Problem
Previously,
PackSolver2scattered decoupling capacitors in irregular patterns, causing overlaps and producing unprofessional-looking schematics. The RP2040 circuit test showed 4 chip overlaps.Solution
This PR adds a specialized linear layout system for decoupling capacitors:
GND) and voltage source nets (V3_3, V1_1, VCC, VDD, VSYS) based on naming conventionsIdentifyDecouplingCapsSolverto follow strong pin connections when determining net connectivitycreateLinearDecouplingCapLayout()method inSingleInnerPartitionPackingSolverthat arranges capacitors in clean horizontal rowsResults
Before:
After:
Test Plan
tsc --noEmit)bun run format:check)Technical Details
The implementation detects decoupling capacitors based on:
When a partition is marked as
partitionType: "decoupling_caps", the solver bypassesPackSolver2and uses the linear layout algorithm instead, arranging components in a horizontal row centered at the origin.Fixes #15
/claim #15