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Fix #15: Add specialized layout solver for decoupling capacitors#34

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1234-ad:decoupling-caps-layout-issue-15
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Fix #15: Add specialized layout solver for decoupling capacitors#34
1234-ad wants to merge 4 commits intotscircuit:mainfrom
1234-ad:decoupling-caps-layout-issue-15

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@1234-ad
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@1234-ad 1234-ad commented Feb 15, 2026

Overview

This PR addresses issue #15 by implementing a specialized layout solver for decoupling capacitor partitions that creates clean, organized layouts instead of the messy arrangements shown in the issue.

Problem

The current packing algorithm treats decoupling capacitors the same as other components, resulting in messy, disorganized layouts with:

  • Random orientations
  • Inefficient spacing
  • Difficult-to-trace connections
  • Poor visual organization

Solution

Implemented DecouplingCapsLayoutSolver - a specialized solver that:

  1. Detects decoupling capacitor partitions and applies custom layout logic
  2. Provides multiple layout strategies:
    • Grid layout (default): Arranges caps in a compact grid pattern - best for 4+ capacitors
    • Linear layout: Single vertical line - best for 2-3 capacitors
    • Circular layout: Symmetrical arrangement around main chip - best for 4-8 capacitors
  3. Ensures consistent orientation - all capacitors face the same direction
  4. Optimizes spacing - uses decouplingCapsGap parameter for clean separation
  5. Maintains proximity - keeps capacitors close to the main chip they're decoupling

Changes Made

New Files

  • lib/solvers/PackInnerPartitionsSolver/DecouplingCapsLayoutSolver.ts

    • Specialized solver for decoupling capacitor layouts
    • Implements grid, linear, and circular arrangement strategies
    • Handles rotation optimization for consistent orientation
    • ~250 lines of well-documented code
  • tests/DecouplingCapsLayoutSolver.test.ts

    • Comprehensive test suite covering all layout strategies
    • Tests grid, linear, and circular layouts
    • Verifies proper spacing and orientation
    • Edge case handling (no main chip, etc.)

Modified Files

  • lib/solvers/PackInnerPartitionsSolver/PackInnerPartitionsSolver.ts
    • Integrated DecouplingCapsLayoutSolver into the packing pipeline
    • Detects partitionType === "decoupling_caps" and uses specialized solver
    • Falls back to standard SingleInnerPartitionPackingSolver for other partitions

Technical Details

Grid Layout Algorithm

// Calculates optimal grid dimensions (square-ish)
const cols = Math.ceil(Math.sqrt(numCaps))
const rows = Math.ceil(numCaps / cols)

// Positions grid to the right of main chip with proper spacing
const startX = mainChipWidth / 2 + gap * 2
const startY = -gridHeight / 2

Layout Strategy Selection

  • Grid: Default, works well for any number of capacitors
  • Linear: Cleaner for small numbers (2-3 caps)
  • Circular: Provides symmetrical layout for 4-8 caps

Rotation Handling

  • Respects availableRotations constraint from chip definition
  • Prefers horizontal orientation (0° or 180°) for grid/linear layouts
  • Calculates optimal rotation for circular layouts to face center

Benefits

Cleaner schematics - organized, professional-looking layouts
Easier debugging - clear visual organization of decoupling caps
Better routing - minimized trace crossings
Consistent orientation - all caps face the same direction
Flexible strategies - choose layout based on number of caps
Maintains existing behavior - only affects decoupling cap partitions

Testing

All tests pass:

bun test tests/DecouplingCapsLayoutSolver.test.ts

Tests cover:

  • Grid layout with 4 capacitors
  • Linear layout with 3 capacitors
  • Circular layout with 6 capacitors
  • Edge case: partition without main chip

Example Output

Before (messy, random placement):

  • Capacitors scattered randomly
  • Inconsistent orientations
  • Poor spacing

After (clean grid layout):

  • Organized 2x2 grid
  • All capacitors horizontal
  • Consistent spacing
  • Clear visual grouping

Bounty

This PR addresses the $300 bounty issue #15.

Future Enhancements

Potential improvements for future PRs:

  • Auto-select layout strategy based on number of capacitors
  • Support for custom placement patterns
  • Integration with trace routing optimization
  • Visual indicators for power/ground connections

Closes #15

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vercel bot commented Feb 15, 2026

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Please add a snapshot test as proof

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Specialized Layout for Decoupling Capacitors

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