target/i386: Decode group 3 /1 instructions as TEST - #2353
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According to table A-6 in Volume 3 of AMD64 Architecture Programmer's Manual, group 3 instructions that have ModRM.reg field value of either 0 or 1 are decoded as TEST instruction. Although Volume 2 of Intel 64 and IA-32 Architectures Software Developer's Manual leaves the cell for ModRM.reg == 1 in group 3 in table A-6 blank, group 3 instructions with ModRM.reg == 1 seem to behave like TEST on Intel CPUs. Currently, Unicorn does not recognize group 3 instruction with ModRM.reg == 1. As a result, it raises an #UD exception. This behavior does not match that of a real hardware. Fix this issue by adding a missing `case 1:` to the group 3 decoder. Upstream QEMU issue: https://gitlab.com/qemu-project/qemu/-/work_items/3580 Signed-off-by: Andrey Polivoda <apolivodaa433@gmail.com>
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According to table A-6 in Volume 3 of AMD64 Architecture Programmer's Manual, group 3 instructions that have ModRM.reg field value of either 0 or 1 are decoded as TEST instruction.
Although Volume 2 of Intel 64 and IA-32 Architectures Software Developer's Manual leaves the cell for ModRM.reg == 1 in group 3 in table A-6 blank, group 3 instructions with ModRM.reg == 1 seem to behave like TEST on Intel CPUs.
Currently, Unicorn does not recognize group 3 instruction with ModRM.reg == 1. As a result, it raises an #UD exception. This behavior does not match that of a real hardware.
Fix this issue by adding a missing
case 1:to the group 3 decoder.Upstream QEMU issue: https://gitlab.com/qemu-project/qemu/-/work_items/3580