target/i386: Reject ModRM.reg == 7 early when decoding 0xFE/0xFF (group 4 and 5) instructions - #2362
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For such instruction semantic related fixes, a unit test could greatly speed up my reviewing process because I can debug and see the difference. Thanks in advance if you wish adding one. |
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Noted. Working on it |
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Added the unit test |
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I see there's a merge conflict in test_x86.c across my open PRs. Please let me know when you are ready to merge each PR, and I'll resolve the conflicts one by one. |
…up 4 and 5) instructions According to both table A-6 in Volume 2 of Intel 64 and IA-32 Architectures Software Developer's Manual and table A-6 in Volume 3 of AMD64 Architecture Programmer's Manual, the opcode for ModRM.reg == 7 is reserved for both group 4 (0xFE) and 5 (0xFF) instructions. Although Unicorn already rejects ModRM.reg == 7 early with group 4 (0xFE) instructions, that is not the case with group 5 (0xFF) instructions. The latter case is eventually handled in the `default:` block of `switch(op)`, but by the time that code is reached, some micro-ops are already generated. These may include a memory load micro-op. As a result, an invalid memory access error may be produced instead of an expected invalid instruction error. Fix this bug by rejecting group 4 and 5 instructions with ModRM.reg == 7 before generating any micro-operations. Signed-off-by: Andrey Polivoda <apolivodaa433@gmail.com>
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Resolved the conflict. Moved the test between existing ones to prevent future conflicts. Also the commit is signed now. |
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According to both table A-6 in Volume 2 of Intel 64 and IA-32 Architectures Software Developer's Manual and table A-6 in Volume 3 of AMD64 Architecture Programmer's Manual, the opcode for ModRM.reg == 7 is reserved for both group 4 (0xFE) and 5 (0xFF) instructions.
Although Unicorn already rejects ModRM.reg == 7 early with group 4 (0xFE) instructions, that is not the case with group 5 (0xFF) instructions. The latter case is eventually handled in the
default:block ofswitch(op), but by the time that code is reached, some micro-ops are already generated. These may include a memory load micro-op. As a result, an invalid memory access error may be produced instead of an expected invalid instruction error.Fix this bug by rejecting group 4 and 5 instructions with ModRM.reg == 7 before generating any micro-operations.