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fix: zero-extend tricore ld.bu(#2348) - #2381

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Jvlegod:fix/tricore-ld-bu-preinc
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fix: zero-extend tricore ld.bu(#2348)#2381
Jvlegod wants to merge 1 commit into
unicorn-engine:devfrom
Jvlegod:fix/tricore-ld-bu-preinc

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@Jvlegod

@Jvlegod Jvlegod commented Aug 7, 2026

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close #2348

verify

from unicorn import *
from unicorn.tricore_const import *
CODE=b"\x09\x2f\x41\x04"  # ld.bu d15, [+a2]0x1
CODE_ADDR=0x10000
DATA_ADDR=0x20000

mu=Uc(UC_ARCH_TRICORE, UC_MODE_LITTLE_ENDIAN)
mu.mem_map(CODE_ADDR, 0x10000)
mu.mem_map(DATA_ADDR, 0x10000)
mu.mem_write(CODE_ADDR, CODE)
mu.mem_write(DATA_ADDR + 1, b"\xbc")
mu.reg_write(UC_TRICORE_REG_A2, DATA_ADDR)
mu.emu_start(CODE_ADDR, CODE_ADDR + len(CODE), count=1)

d15=mu.reg_read(UC_TRICORE_REG_D15)
a2=mu.reg_read(UC_TRICORE_REG_A2)

print(f"D15=0x{d15:08x}")
print(f"A2=0x{a2:08x}")
assert d15 == 0x000000bc
assert a2 == DATA_ADDR + 1

Expected output:

D15=0x000000bc
A2=0x00020001

Also tests #2348:

Output:

ld.bu d0,[a15]      -> 0x00000080
ld.bu d15,[+a2]0x1  -> 0x000000BC

@Jvlegod
Jvlegod force-pushed the fix/tricore-ld-bu-preinc branch from 4869d09 to 26be46b Compare August 7, 2026 06:47
@PhilippTakacs

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can you add your test to tests/unit/test_tricore.c?

Signed-off-by: Jvle <keke.oerv@isrc.iscas.ac.cn>
@Jvlegod
Jvlegod force-pushed the fix/tricore-ld-bu-preinc branch from 26be46b to 8ff3bcb Compare August 7, 2026 13:33
@Jvlegod

Jvlegod commented Aug 7, 2026

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can you add your test to tests/unit/test_tricore.c?

sure, I have add tests.

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2 participants