riscv: gate counter CSRs on mcounteren at every priv version - #2392
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carlosqwqqwq wants to merge 1 commit into
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riscv: gate counter CSRs on mcounteren at every priv version#2392carlosqwqqwq wants to merge 1 commit into
carlosqwqqwq wants to merge 1 commit into
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riscv: gate counter CSRs on
mcounterenat every priv versionFixes #2387
Problem
The
ctrpredicate returns success for every counter CSR whenpriv_ver > 1.09, so U/S-modehpmcounter*(andcycle/time/instret) reads retire even withmcounteren=0. The enabling comment confusesmcounteren(readability) withmcountinhibit(incrementing).Change
qemu/target/riscv/csr.cctr(): remove thepriv_ver > PRIV_VERSION_1_09_1early-success branch so themcounteren/scounterenchecks apply at every priv version, mirroring upstream QEMU master. The proposed change is source-only and contains no test-framework or repository-local changes.Regression scope
Verify that M-mode counter access is unaffected, S/U-mode accesses are gated by
mcounteren/scounteren, and existing counter and CSR tests remain unchanged.