riscv: gate fsgnj.d/fmv.d on FPU and D extension - #2393
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riscv: gate
fsgnj.d/fmv.don FPU and D extensionFixes #2388
Problem
trans_fsgnj_dlacksREQUIRE_FPUandREQUIRE_EXT(ctx, RVD), sofsgnj.d/fmv.dretire on CPU models without F/D (e.g. SiFive E51) instead of raising an illegal-instruction trap.Change
qemu/target/riscv/insn_trans/trans_rvd.inc.ctrans_fsgnj_d: addREQUIRE_FPU; REQUIRE_EXT(ctx, RVD);at the top, matching every other D-extension translation in the same file.The proposed change is source-only and contains no test-framework or repository-local changes.
Regression scope
Verify that
fsgnj.dtraps on a CPU without F/D and still executes correctly on a CPU with D, and that the existing floating-point tests remain unchanged.