riscv: reject odd instruction addresses at fetch time - #2394
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riscv: reject odd instruction addresses at fetch time
Fixes #2390
Problem
IALIGN=16 forbids instruction addresses with bit 0 set (even with the C extension). Unicorn accepts an externally supplied odd PC at the emulator entry and fetches at that address; branch-target checks in
trans_rvi.inc.cdo not cover the entry path.Change
qemu/target/riscv/translate.criscv_tr_translate_insn: whenctx->base.pc_next & 1, raiseRISCV_EXCP_INST_ADDR_MIS(throughgen_exception_inst_addr_mis, which also records the address inmtval) before any fetch. The proposed change is source-only and contains no test-framework or repository-local changes.Regression scope
Verify that starting at an odd PC raises the instruction-address-misaligned exception on both C and non-C models, that even-PC starts and all legal compressed/32-bit streams are unaffected, and that existing tests remain unchanged.