riscv: gate D-width atomic translators on the A extension - #2395
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carlosqwqqwq wants to merge 1 commit into
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riscv: gate D-width atomic translators on the A extension#2395carlosqwqqwq wants to merge 1 commit into
carlosqwqqwq wants to merge 1 commit into
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riscv: gate D-width atomic translators on the A extension
Fixes #2389
Problem
The eleven RV64 D-width atomic translators in
trans_rva.inc.c(trans_lr_d,trans_sc_d,trans_amoswap_d,trans_amoadd_d,trans_amoxor_d,trans_amoand_d,trans_amoor_d,trans_amomin_d,trans_amomax_d,trans_amominu_d,trans_amomaxu_d) emit their memory operations without theREQUIRE_EXT(ctx, RVA)check that every W-width sibling performs, so they retire and modify memory on harts without A instead of raising an illegal-instruction exception.Change
Add
REQUIRE_EXT(ctx, RVA);as the first statement of each of the eleven D-width translators. The check readsctx->misa & RVA; a hart with MISA bit 0 clear now traps at the first D-width atomic before any memory effect, matching the W-width translators and upstream QEMU. The proposed change is source-only and contains no test-framework or repository-local changes.Regression scope
The regression must verify that
lr.d/sc.d/amo*.draise an illegal-instruction exception on a no-A model (and that the W-width control still traps), and that the same instructions still retire on models with A (E51/U54) and on the A-enabled default model. Existing atomic and AMO tests must remain unchanged.